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56f8300 16-bit digital signal controllers freescale.com 56f8366/56f8166 data sheet preliminary technical data mc56f8366 rev. 2.0 07/2005
56f8366 technical data, rev. 2.0 2 freescale semiconductor preliminary document revision history version history description of change rev 0 pre-release, alpha customers only rev 1.0 initial public release rev. 2.0 added output voltage maximum value and note to clarify in table 10-1 ; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. clarified value and unit measure for maximum allowed p d in table 10-3 . corrected note about average value for flash data retention in table 10-4 . added new rohs-compliant orderable part numbers in table 13-1 . please see http://www.freescale.com for the most current data sheet revision.
56f8366 technical data, rev. 2.0 freescale semiconductor 3 preliminary 56f8366/56f8166 block diagram - 144 lqfp program controller and hardware looping unit data alu 16 x 16 + 36 -> 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit pll clock generator extal interrupt controller cop/ watchdog sci1 or gpiod 4 external address bus switch external bus interface unit 2 clkmode irqa irqb external data bus switch program memory 256k x 16 flash 2k x 16 ram boot rom 16k x 16 flash d ata memory 16k x 16 flash 16k x 16 ram pdb pdb xab1 xab2 xdb2 cdbr sci0 or gpioe spi0 or gpioe ipbus bridge (ipbb) integration module system p o r o s c decoding peripherals peripheral device selects rw control ipab ipwdb iprdb 2 system bus r/w control memory pab pab cdbw cdbr cdbw clock resets jtag/ eonce port digital reg analog reg low voltage supervisor v cap v dd v ss v dda v ssa 5 47 52 v pp 2 ocr_dis reset extboot emi_mode rsto 4 3 6 pwm outputs fault inputs pwma current sense inputs or gpioc 3 4 6 pwm outputs fault inputs pwmb current sense inputs or gpiod 3 quad timer d or gpioe quad timer c or gpioe ad0 ad1 adca 2 5 quadrature decoder 0 or quad timer a or gpioc flexcan 2 4 ad0 ad1 4 4 4 temp_sense quadrature decoder 1 or quad timer b or spi1 or gpioc 4 clko bus control 6 2 8 7 9 xtal ps / cs0 (gpiod8) rd wr d7-15 or gpiof0-8 d0-6 or gpiof9-15 gpiob0 or a16 a8-15 or gpioa0-7 a0-5 or gpioa8-13 a6-7 or gpioe2-3 vref adcb 16-bit 56800e core ds / cs1 (gpiod9) control gpio or emi cs or flexcan2 gpiod1 (cs3 or can2_rx) gpiod0 (cs 2 or can2_tx) 56f8366/56f8166 general description note: features in italics are not available in the 56f8166 device. ? up to 60 mips at 60mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? access up to 1mb of off-chip program and data memory ? chip select logic for glueless interface to rom and sram ? 512kb of program flash ? 4kb of program ram ? 32kb of data flash ? 32kb of data ram ? 32kb of boot flash ? up to two 6-channel pwm modules ? four 4-channel, 12-bit adcs ? temperature sensor ? up to two quadrature decoders ? optional on-chip regulator ? up to two flexcan modules ? two serial communication interfaces (scis) ? up to two serial peripheral interfaces (spis) ? up to four general purpose quad timers ? computer operating properly (cop) / watchdog ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ? up to 62 gpio lines ? 144-pin lqfp package
56f8366 technical data, rev. 2.0 4 freescale semiconductor preliminary part 1: overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56f8366/56f8166 features . . . . . . . . . . . . . 5 1.2. device description . . . . . . . . . . . . . . . . . . . . 7 1.3. award-winning development environment . 9 1.4. architecture block diagram . . . . . . . . . . . . 10 1.5. product documentation . . . . . . . . . . . . . . . 14 1.6. data sheet conventions . . . . . . . . . . . . . . 14 part 2: signal/connection descriptions . . . 15 2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. signal pins . . . . . . . . . . . . . . . . . . . . . . . . . 18 part 3: on-chip clock synthesis (occs) . . 38 3.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.2. external clock operation . . . . . . . . . . . . . . 38 3.3. registers . . . . . . . . . . . . . . . . . . . . . . . . . . 40 part 4: memory map . . . . . . . . . . . . . . . . . . . 40 4.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2. program map . . . . . . . . . . . . . . . . . . . . . . . 41 4.3. interrupt vector table . . . . . . . . . . . . . . . . . 44 4.4. data map . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5. flash memory map . . . . . . . . . . . . . . . . . . . 48 4.6. eonce memory map . . . . . . . . . . . . . . . . . 49 4.7. peripheral memory mapped registers . . . . 50 4.8. factory programmed memory . . . . . . . . . . 83 part 5: interrupt controller (itcn) . . . . . . . . 83 5.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.3. functional description . . . . . . . . . . . . . . . . 83 5.4. block diagram . . . . . . . . . . . . . . . . . . . . . . 85 5.5. operating modes . . . . . . . . . . . . . . . . . . . . 85 5.6. register descriptions . . . . . . . . . . . . . . . . . 86 5.7. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 part 6: system integration module (sim) . 114 6.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3. operating modes . . . . . . . . . . . . . . . . . . . 115 6.4. operating mode register . . . . . . . . . . . . . 116 6.5. register descriptions . . . . . . . . . . . . . . . . 117 6.6. clock generation overview . . . . . . . . . . . 132 6.7. power-down modes overview . . . . . . . . . 132 6.8. stop and wait mode disable function . . . 133 6.9. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 part 7: security features . . . . . . . . . . . . . . 134 7.1. operation with security enabled . . . . . . . 134 7.2. flash access blocking mechanisms . . . . 135 part 8: general purpose input/output (gpio) . . . . . . . . . . . . . . . . . . . . . . 137 8.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . 137 8.2. memory maps . . . . . . . . . . . . . . . . . . . . . . 138 8.3. configuration . . . . . . . . . . . . . . . . . . . . . . . 138 part 9: joint test action group (jtag) . 143 9.1. jtag information . . . . . . . . . . . . . . . . . . . .143 part 10: specifications . . . . . . . . . . . . . . . 144 10.1. general characteristics . . . . . . . . . . . . . .144 10.2. dc electrical characteristics . . . . . . . . . . 148 10.3. ac electrical characteristics . . . . . . . . . . 152 10.4. flash memory characteristics . . . . . . . . . 152 10.5. external clock operation timing . . . . . . . 153 10.6. phase locked loop timing . . . . . . . . . . .153 10.7. crystal oscillator timing . . . . . . . . . . . . . 154 10.8. external memory interface timing . . . . . .154 10.9. reset, stop, wait, mode select, and interrupt timing . . . . . . . . . . . . . . 157 10.10. serial peripheral interface (spi) timing . 159 10.11. quad timer timing . . . . . . . . . . . . . . . . 162 10.12. quadrature decoder timing . . . . . . . . . . 163 10.13. serial communication interface (sci) timing . . . . . . . . . . . . . . . . . . . . . 164 10.14. controller area network (can) timing . 164 10.15. jtag timing . . . . . . . . . . . . . . . . . . . . . 165 10.16. analog-to-digital converter (adc) parameters . . . . . . . . . . . . . . . . . 166 10.17. equivalent circuit for adc inputs . . . . . .169 10.18. power consumption . . . . . . . . . . . . . . . . 169 part 11: packaging . . . . . . . . . . . . . . . . . . 171 11.1. 56f8366 package and pin-out information . . . . . . . . . . . . . . . . . . 171 11.2. 56f8166 package and pin-out information . . . . . . . . . . . . . . . . . . 174 part 12: design considerations . . . . . . . . 178 12.1. thermal design considerations . . . . . . . . 178 12.2. electrical design considerations . . . . . . . 179 12.3. power distribution and i/o ring implementation . . . . . . . . . . . . . .180 part 13: ordering information . . . . . . . . . 181 table of contents
56f8366/56f8166 features 56f8366 technical data, rev. 2.0 freescale semiconductor 5 preliminary part 1 overview 1.1 56f8366/56f8166 features 1.1.1 core ? efficient 16-bit 56800e family controller engine with dual harvard architecture ? up to 60 million instructions per second (mips) at 60mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? arithmetic and logic multi-bit shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/eonce debug programming interface 1.1.2 differences between devices table 1-1 outlines the key differences be tween the 56f8366 and 56f8166 devices. table 1-1 device differences feature 56f8366 56f8166 guaranteed speed 60mhz/60 mips 40mhz/40 mips program ram 4kb not available data flash 8kb not available pwm 2 x 6 1 x 6 can 2 not available quad timer 4 2 quadrature decoder 2 x 4 1 x 4 temperature sensor 1 not available dedicated gpio ? 5
56f8366 technical data, rev. 2.0 6 freescale semiconductor preliminary 1.1.3 memory note: features in italics are not available in the 56f8166 device. ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? flash security protection feature ? on-chip memory, including a low-cost, high-volume flash solution ? 512kb of program flash ? 4kb of program ram ? 32kb of data flash ?32kb of data ram ? 32kb of boot flash ? off-chip memory expansion capabilities programmable for 0 - 30 wait states ? access up to 1mb of program memory or 1mb of data memory ? chip select logic for glueless interface to rom and sram ? eeprom emulation capability 1.1.4 peripheral circuits for 56f8366 note: features in italics are not available in the 56f8166 device. ? pulse width modulator: ? in the 56f8366, two pulse width modulator modules, each with six pwm outputs, three current sense inputs, and three fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes ? in the 56f8166, one pulse width modulator module with six pwm outputs, three current sense inputs, and three fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes ? four 12-bit, analog-to-digital converters (adcs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; adc and pwm modules can be synchronized through timer c, channels 2 and 3 ? quadrature decoder: ? in the 56f8366, two four-input quadrature decoders or two additional quad timers ? in the 56f8166, one four-input quadrature decoder, which works in conjunction with quad timer a ? temperature sensor diode can be connected, on the board, to any of the adc inputs to monitor the on-chip temperature ? quad timer: ? in the 56f8366, four dedicated general-purpose quad timers totaling three dedicated pins: timer c with one pin and timer d with two pins ? in the 56f8166, two quad timers; timer a and timer c both work in conjunction with gpio ? optional on-chip regulator ? up to two flexcan (can version 2.0 b-compliant ) modules with 2-pin port for transmit and receive
device description 56f8366 technical data, rev. 2.0 freescale semiconductor 7 preliminary ? two serial communication interfaces (scis), each with two pins (or four additional gpio lines) ? up to two serial peripheral interfaces (spis), both with configurable 4-pin port (or eight additional gpio lines) ? in the 56f8366, spi1 can also be used as quadrature decoder 1 or quad timer b ? in the 56f8166, spi1 can alternately be used only as gpio ? computer operating properly (cop) / watchdog timer ? two dedicated external interrupt pins ? 62 general purpose i/o (gpio) pins ? external reset input pin for hardware reset ? external reset output pin for system reset ? integrated low-voltage interrupt module ? jtag/enhanced on-chip emulation (once) for unobtrusive, processor speed-independent, real-time debugging ? software-programmable, phase lock loop (pll)-based frequency synthesizer for the core clock 1.1.5 energy information ? fabricated in high-density cmos with 5v-tolerant, ttl-compatible digital inputs ? on-board 3.3v down to 2.6v voltage regulator for powering internal logic and memories; can be disabled ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? adc smart power management ? each peripheral can be individually disabled to save power 1.2 device description the 56f8366 and 56f8166 are members of the 56800e core-based family of controllers. each combines, on a single chip, the processing power of a digital signal processor (dsp) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the 56f8366 and 56f8166 are well-suited for many applications. the devices include many peripherals that are especially useful for motion control, smart appliances, steppers, encode rs, tachometers, limit switches, power supply and control, automotive control (56f8366 only), engine manage ment, noise suppression, remote utility metering, industrial control for power, lighting, and automation applications. the 56800e core is based on a harvard-style architect ure consisting of three execution units operating in parallel, allowing as many as six operations per inst ruction cycle. the mcu-style programming model and optimized instruction set allow straightforward gene ration of efficient, compact dsp and control code. the instruction set is also highly efficient for c/c++ compilers to enable rapid development of optimized control applications. the 56f8366 and 56f8166 support program execution from either internal or external memories. two data operands can be accessed from the on-chip da ta ram per instruction cycle. these devices also provides two external dedicated interrupt lines and up to 62 general purpose input/output (gpio) lines, depending on peripheral configuration.
56f8366 technical data, rev. 2.0 8 freescale semiconductor preliminary 1.2.1 56f8366 features the 56f8366 hybrid controller includes 512kb of pr ogram flash and 32kb of data flash (each programmable through the jtag port) with 4kb of program ram and 32kb of data ram. it also supports program execution from external memory. a total of 32kb of boot flash is incorporated for ea sy customer inclusion of field-programmable software routines that can be used to program the main progr am and data flash memory areas. both program and data flash memories can be independently bulk erased or erased in pages. program flash page erase size is 1kb. boot and data flash page erase size is 512 bytes. the boot flash memory can also be either bulk or page erased. a key application-specific feature of the 56f8366 is the inclusion of two pulse width modulator (pwm) modules. these modules each incorporate three complementary, individually programmable pwm signal output pairs (each module is also capable of supporti ng six independent pwm functions, for a total of 12 pwm outputs) to enhance motor control functional ity. complementary operation permits programmable dead time insertion, distortion correction via curren t sensing by software, and separate top and bottom output polarity control. the up-counter value is pr ogrammable to support a c ontinuously variable pwm frequency. edge-aligned and center-a ligned synchronous pulse width cont rol (0% to 100% modulation) is supported. the device is capable of controlling most motor types: acim (ac induction motors); both bdc and bldc (brush and brushless dc motors); srm and vrm (switched and variable reluctance motors); and stepper motors. the pwms incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to direc tly drive standard optoisolators. a ?smoke-inhibit?, write-once protection feature for key parameters is also included. a patented pwm waveform distortion correction circuit is also provided. each pwm is doubl e-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. the pwm modules provide reference outputs to synchronize the analog-to-digital converter s through two channels of quad timer c. the 56f8366 incorporates two quadrature decoders ca pable of capturing all four transitions on the two-phase inputs, permitting genera tion of a number proportional to ac tual position. speed computation capabilities accommodate both fast- and slow-movi ng shafts. an integrated watchdog timer in the quadrature decoder can be programmed with a time-out value to alert when no shaft motion is detected. each input is filtered to ensure only true transitions are recorded. this controller also provides a full set of standa rd programmable peripherals that include two serial communications interfaces (scis), tw o serial peripheral interfaces (spi s), and four quad timers. any of these interfaces can be used as general-purpose i nput/outputs (gpios) if that function is not required. two flex controller area network (flexcan) interf aces (can version 2.0 b-compliant) and an internal interrupt controller are included on the 56f8366. 1.2.2 56f8166 features the 56f8166 hybrid controller includes 512kb of pr ogram flash, programmable through the jtag port, with 32kb of data ram. it also supports program execution from external memory. a total of 32kb of boot flash is incorporated for ea sy customer inclusion of field-programmable software routines that can be used to program the main pr ogram flash memory area, which can be independently
award-winning development environment 56f8366 technical data, rev. 2.0 freescale semiconductor 9 preliminary bulk erased or erased in pages. program flash page er ase size is 1kb. boot flash page erase size is 512 bytes and the boot flash memory can also be either bulk or page erased. a key application-specific feature of the 56f8166 is the inclusion of one pulse width modulator (pwm) module. this module incorporates three compleme ntary, individually progra mmable pwm signal output pairs and can also support six independent pwm f unctions to enhance motor control functionality. complementary operation permits pr ogrammable dead time insertion, di stortion correction via current sensing by software, and separate top and bottom output polarity control. the up-counter value is programmable to support a continuously variable pwm frequency. edge-aligned and center-aligned synchronous pulse width control (0% to 100% modul ation) is supported. the device is capable of controlling most motor types: acim (ac induction mo tors); both bdc and bldc (brush and brushless dc motors); srm and vrm (switched and variable reluctance motors); and stepper motors. the pwm incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. a ?smoke-inhi bit?, write-once protection feature for key parameters is also included. a patented pwm waveform distorti on correction circuit is also provided. each pwm is double-buffered and includes interrupt c ontrols to permit integral reload rates to be programmable from 1 to 16. the pwm module provides reference outputs to synchronize the analog-to-digital converters through two channels of quad timer c. the 56f8166 incorporates a quadrature decoder capable of capturing all four tr ansitions on the two-phase inputs, permitting generation of a number proportional to actual posit ion. speed computation capabilities accommodate both fast- and slow-moving shafts. an integrated watchdog timer in the quadrature decoder can be programmed with a time-out value to alert when no shaft motion is detected. each input is filtered to ensure only true transitions are recorded. this controller also provides a full set of standa rd programmable peripherals that include two serial communications interfaces (scis); two serial periphe ral interfaces (spis); and two quad timers. any of these interfaces can be used as general purpose i nput/outputs (gpios) if that function is not required. an internal interrupt controller is also a part of the 56f8166. 1.3 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software application cr eation with an expert knowledge system. the codewarrior integrated development environmen t is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluati on modules (evms) and development system cards will support concurrent engineering. together, pe, codewarrior and evms create a complete, scalable tools solution for easy, fast, and efficient development.
56f8366 technical data, rev. 2.0 10 freescale semiconductor preliminary 1.4 architecture block diagram note: features in italics are not available in the 56f8166 device and are shaded in the following figures. the 56f8366/56f8166 architecture is shown in figure 1-1 and figure 1-2 . figure 1-1 illustrates how the 56800e system buses communicate with internal memo ries, the external memory interface and the ipbus bridge. table 1-2 lists the internal buses in the 56800e architecture and provides a brief description of their function. figure 1-2 shows the peripherals and control blocks connected to the ipbus bridge. the figures do not show the on-board regulator and power and ground signals. they also do not show the multiplexing between peripherals or the dedicated gpios. please see part 2, signal/connection descriptions, to see which signals are multiplexed with those of other peripherals. also shown in figure 1-2 are connections between the pwm, timer c and adc blocks. these connections allow the pwm and/or timer c to contro l the timing of the start of adc conversions. the timer c channel indicated can generate periodic start (sync) signals to the adc to start its conversions. in another operating mode, the pwm load interrupt (sync output) signal is routed internally to the timer c input channel as indicated. the timer can then be used to introduce a controllable delay before generating its output signal. the timer output then tri ggers the adc. to fully understand this interaction, please see the 56f8300 peripheral user manual for clarification on the operation of all three of these peripherals.
architecture block diagram 56f8366 technical data, rev. 2.0 freescale semiconductor 11 preliminary figure 1-1 system bus interfaces note: flash memories are encapsulated within the flash memory (fm) module. flash control is accomplished by the i/o to the fm over the peripheral bus, while reads and writes are completed between the core and the flash memories. note: the primary data ram port is 32 bits wide. other data ports are 16 bits. program ram 56800e program flash data ram emi data flash ipbus bridge boot flash flash memory module chip tap controller tap linking module jtag / eonce 5 pab[20:0] pdb_m[15:0] cdbw[31:0] xab1[23:0] xab2[23:0] cdbr_m[31:0] xdb2_m[15:0] 17 16 6 external jtag port to flash con trol logic ipbus data address control not available on the 56f8166 device.
56f8366 technical data, rev. 2.0 12 freescale semiconductor preliminary figure 1-2 peripheral subsystem timer a timer c timer d spi 1 adcb adca flexcan gpioa spi0 sci0 sci1 interrupt controller pwma pwmb quadrature decoder 0 note: adca and adcb use the same voltage reference circuit with v refh , v refp, v refmid , v refn , and v reflo pins. gpiob gpioc gpiod gpioe gpiof timer b quadrature decoder 1 temp_sense clkgen (osc/pll) por & lvi sim flexcan2 low voltage interrupt system por cop reset reset cop 2 2 13 12 1 ch3i ch2i ch2o ch3o 8 8 1 4 ipbus 2 2 4 4 2 t o /f rom ipb us b r id ge not available on the 56f8166 device.
architecture block diagram 56f8366 technical data, rev. 2.0 freescale semiconductor 13 preliminary table 1-2 bus signal names name function program memory interface pdb_m[15:0] program data bus for instruction word fetches or read operations. cdbw[15:0] primary core data bus used for program memory writes. (only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] program memory address bus. data is returned on pdb_m bus. primary data memory interface bus cdbr_m[31:0] primary core data bus for memory reads. addressed via xab1 bus. cdbw[31:0] primary core data bus for memory writes. addressed via xab1 bus. xab1[23:0] primary data address bus. capable of addressing bytes 1 , words, and long data types. data is written on cdbw and returned on cdbr_m. also used to access memory-mapped i/o. 1. byte accesses can only occur in the bottom half of the memory address space. the msb of the address will be forced to 0. secondary data memory interface xdb2_m[15:0] secondary data bus used for secondary data address bus xab2 in the dual memory reads. xab2[23:0] secondary data address bus used for the second of two simultaneous accesses. capable of addressing only words. data is returned on xdb2_m. peripheral interface bus ipbus [15:0] peripheral bus accesses all on-chip peripherals registers. this bus operates at the same clock rate as the primary data memory and therefore generates no delays when accessing the processor. write data is obtained from cdbw. read data is provided to cdbr_m.
56f8366 technical data, rev. 2.0 14 freescale semiconductor preliminary 1.5 product documentation the documents in table 1-3 are required for a complete desc ription and proper design with the 56f8366/56f8166 devices. documentation is available from local freescale distributors, freescale semiconductor sales offices, freescale litera ture distribution centers, or online at http://www.freescale.com. table 1-3 chip documentation 1.6 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, and 16-bit controller core processor and the instruction set dsp56800erm 56f8300 peripheral user manual detailed description of peripherals of the 56f8300 devices mc56f8300um 56f8300 sci/can bootloader user manual detailed description of the sci/can bootloaders 56f8300 family of devices mc56f83xxblum 56f8366/56f8166 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8366 56f8366 errata details any chip issues that might be present mc56f8366e mc56f8166e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. ?asserted? a high true (active high) signal is high or a low true (active low) signal is low. ?deasserted? a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for vil, vol, vih, and voh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
introduction 56f8366 technical data, rev. 2.0 freescale semiconductor 15 preliminary part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f8366 and 56f8166 are organized into functional groups, as detailed in table 2-1 and as illustrated in figure 2-1 . in table 2-2 , each table row describes the signal or signals present on a pin. table 2-1 functional group pin allocations functional group number of pins in package 56f8366 56f8166 power (v dd or v dda )99 power option control 1 1 ground (v ss or v ssa )66 supply capacitors 1 & v pp 1. if the on-chip regulator is disabled, the v cap pins serve as 2.5v v dd_core power inputs 66 pll and clock 4 4 address bus 17 17 data bus 16 16 bus control 6 6 interrupt and program control 6 6 pulse width modulator (pwm) ports 25 13 serial peripheral interface (spi) port 0 4 4 serial peripheral interface (spi) port 1 ? 4 quadrature decoder port 0 2 2. alternately, can function as quad timer pins or gpio 44 quadrature decoder port 1 3 3. pins in this section can function as quad timer, spi #1, or gpio 4? serial communications interface (sci) ports 4 4 can ports 2 ? analog to digital converter (adc) ports 21 21 quad timer module ports 3 1 jtag/enhanced on-chip emulation (eonce) 5 5 temperature sense 1 ? dedicated gpio ? 5
56f8366 technical data, rev. 2.0 16 freescale semiconductor preliminary figure 2-1 56f8366 signals identified by functional group 1 (144-pin lqfp) 1. alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. v dd_io v dda_adc v ss v ssa_adc other supply ports pll and clock external address bus or gpio external data bus or gpio sci 0 or gpio sci 1 or gpio 1 7 1 5 v pp 1 & v pp 2 2 power ground power ground a8 - a15 (gpioa0 - 7) txd0 (gpioe0) rxd0 (gpioe1) txd1 (gpiod6) rxd1 (gpiod7) tck tms tdi tdo trst quadrature decoder 0 or quad timer a or gpio phasea0 (ta0, gpioc4) phaseb0 (ta1, gpioc5) index0 (ta2, gpioc6) home0 (ta3, gpioc7) phaseb1 (tb1, mosi1, gpioc1) index1 (tb2, miso1, gpioc2) home1 (tb3, ss1 , gpioc3) pwma0 - 5 isa0 - 2 (gpioc8 - 10) faulta0 - 2 isb0 - 2 (gpiod10 - 12) faultb0 - 3 pwmb0 - 5 ana0 - 7 anb0 - 7 v ref can_rx can_tx tc0 (gpioe8) td0 - 1 (gpioe10 - 11) irqa irqb reset rsto spi0 or gpio pwma or gpio quadrature decoder 1 or quad timer b or spi 1 or gpio pwmb or gpio adcb adca flexcan quad timer c and d or gpio interrupt/ program control phasea1(tb0, sclk1, gpioc0) 8 1 gpiob0 (a16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 3 3 6 3 4 8 5 8 1 1 1 1 2 1 1 1 1 1 56f8366 temp_sense extal xtal clko 1 1 1 v cap 1 - v cap 4 4 a0 - a5 (gpioa8 - 13) 6 a6 - a7 (gpioe2 - 3) 2 rd 1 wr 1 ps / cs0 (gpiod8) 1 ds / cs1 (gpiod9) 1 gpiod0 (cs2 , can2_tx) 1 jtag/ eonce port external bus control or gpio d7 - d15 (gpiof0 - 8) 9 d0 - d6 (gpiof9 - 15) 7 extboot mosi0 (gpioe5) miso0 (gpioe6) ss0 (gpioe7) 1 1 1 sclk0 (gpioe4) 1 1 emi_mode ocr_dis 1 power clkmode 1 v dda_osc_pll 1 temperature sensor 1 gpiod1 (cs3 , can2_rx
introduction 56f8366 technical data, rev. 2.0 freescale semiconductor 17 preliminary figure 2-2 56f8166 signals identified by functional group 1 (144-pin lqfp) 1. alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. v dd_io v dda_adc v ss v ssa_adc other supply ports pll and clock external address bus or gpio external data bus or gpio sci 0 or gpio sci 1 or gpio 1 7 1 5 v pp 1 & v pp 2 2 power ground power ground a8 - a15 (gpioa0 - 7) txd0 (gpioe0) rxd0 (gpioe1) txd1 (gpiod6) rxd1 (gpiod7) tck tms tdi tdo trst quadrature decoder 0 or quad timer a or gpio phasea0 (ta0, gpioc4) phaseb0 (ta1, gpioc5) index0 (ta2, gpioc6) home0 (ta3, gpioc7) (mosi1, gpioc1) (miso1, gpioc2) (s s1 , gpioc3) (gpioc8 - 10) isb0 - 2 (gpiod10 - 12) faultb0 - 3 pwmb0 - 5 ana0 - 7 anb0 - 7 v ref tc0 (gpioe8) (gpioe10 - 11) irqa irqb reset rsto spi0 or gpio spi 1 or gpio pwmb or gpio adcb adca quad timer c or gpio interrupt/ program control (sclk1, gpioc0) 8 1 gpiob0 (a16) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 6 3 4 8 5 8 1 2 1 1 1 1 1 56f8166 extal xtal clko 1 1 1 v cap 1 - v cap 4 4 a0 - a5 (gpioa8 - 6 a6 - a7 (gpioe2 - 3) 2 rd 1 wr 1 ps (cs0 )(gpiod8) 1 ds (cs1) (gpiod9) 1 gpiod0 - 1 (cs2 - 3 ) 2 jtag/ eonce port external bus control or gpio d7 - d15 (gpiof0 - 9 d0-d6 (gpiof9 - 15) 7 extboot mosi0 miso0 ss0 (gpioe7) 1 1 1 sclk0 1 1 emi_mode ocr_dis 1 power clkmode 1 v dda_osc_pll 1 gpio
56f8366 technical data, rev. 2.0 18 freescale semiconductor preliminary 2.2 signal pins after reset, each pin is configured for its primary f unction (listed first). any alternate functionality must be programmed. note: signals in italics are not available in the 56f8166 device. if the ?state during reset? lists more than one state for a pin, the first state is the actual reset state. other states show the reset condition of the alternate f unction, which you get if the alternate pin function is selected without changing the configuration of the a lternate peripheral. for example, the a8/gpioa0 pin shows that it is tri-stated during reset. if the gpio a_per is changed to select the gpio function of the pin, it will become an input if no other registers are changed. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description v dd_io 1 supply i/o power ? this pin supplies 3.3v power to the chip i/o interface and also the processor core throught the on-chip voltage regulator, if it is enabled. v dd_io 16 v dd_io 31 v dd_io 38 v dd_io 66 v dd_io 84 v dd_io 119 v dda_adc 102 supply adc power ? this pin supplies 3.3v power to the adc modules. it must be connected to a clean analog power supply. v dda_osc_pll 80 supply oscillator and pll power ? this pin supplies 3.3v power to the osc and to the internal regulator that in turn supplies the phase locked loop. it must be connected to a clean analog power supply. v ss 27 supply v ss ? these pins provide ground for chip logic and i/o drivers. v ss 37 v ss 63 v ss 69 v ss 144
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 19 preliminary v ssa_adc 103 supply adc analog ground ? this pin supplies an analog ground to the adc modules. ocr_dis 79 input input on-chip regulator disable ? tie this pin to v ss to enable the on-chip regulator tie this pin to v dd to disable the on-chip regulator this pin is intended to be a static dc signal from power-up to shut down. do not try to toggle this pin for power savings during operation. v cap 1 51 supply supply v cap 1 - 4 ? when ocr_dis is tied to v ss (regulator enabled), connect each pin to a 2.2 f or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. when ocr_dis is tied to v dd (regulator disabled), these pins become v dd_core and should be connected to a regulated 2.5v power supply. note: this bypass is required even if the chip is powered with an external supply. v cap 2 128 v cap 3 83 v cap 4 15 v pp 1 125 input input v pp 1 - 2 ? these pins should be left unconnected as an open circuit for normal functionality. v pp 2 2 clkmode 87 input input clock input mode selection ? this input determines the function of the xtal and extal pins. 1 = external clock input on xtal is used to directly drive the input clock of the chip. the extal pin should be grounded. 0 = a crystal or ceramic resonator should be connected between xtal and extal. extal 82 input input external crystal oscillator input ? this input can be connected to an 8mhz external crystal. tie this pin low if xtal is driven by an external clock source. xtal 81 input/ output chip-driven crystal oscillator output ? this output connects the internal crystal oscillator output to an external crystal. if an external clock is used, xtal must be used as the input and extal connected to gnd. the input clock can be selected to provide the clock directly to the core. this input clock can also be selected as the input clock for the on-chip pll. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 20 freescale semiconductor preliminary clko 3 output tri-stated clock output ? this pin outputs a buffered clock signal. using the sim clko select register (sim_clkosr), this pin can be programmed as any of the following: disabled, clk_mstr (system clock), ipbus clock, oscillator output, prescaler clock and postscaler clock. other signals are also available for test purposes. see part 6.5.7 for details. a0 (gpioa8) 138 output input/ output tri-stated input address bus ? a0 - a5 specify six of the address lines for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), a0?a5 and emi control signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port a gpio ? these six gpio pins can be individually programmed as input or output pins. after reset, the default state is address bus. to deactivate the internal pull-up resistor, set the appropriate gpio bit in the gpioa_pur register. example: gpioa8, set bit 8 in the gpioa_pur register. a1 (gpioa9) 10 a2 (gpioa10) 11 a3 (gpioa11) 12 a4 (gpioa12) 13 a5 (gpioa13) 14 table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 21 preliminary a6 (gpioe2) 17 output schmitt input/ output tri-stated input address bus ? a6 - a7 specify two of the address lines for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), a6?a7 and emi control signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port e gpio ? these two gpio pins can be individually programmed as input or output pins. after reset, the default state is address bus. to deactivate the internal pull-up resistor, set the appropriate gpio bit in the gpioe_pur register. example: gpioe2, set bit 2 in the gpioe_pur register. a7 (gpioe3) 18 a8 (gpioa0) 19 output schmitt input/ output tri-stated input address bus ? a8 - a15 specify eight of the address lines for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), a8?a15 and emi control signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port a gpio ? these eight gpio pins can be individually programmed as input or output pins. after reset, the default state is address bus. to deactivate the internal pull-up resistor, set the appropriate gpio bit in the gpioa_pur register. example: gpioa0, set bit 0 in the gpioa_pur register. a9 (gpioa1) 20 a10 (gpioa2) 21 a11 (gpioa3) 22 a12 (gpioa4) 23 a13 (gpioa5) 24 a14 (gpioa6) 25 a15 (gpioa7) 26 table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 22 freescale semiconductor preliminary gpiob0 (a16) 33 schmitt input/ output output input tri-stated port b gpio ? this gpio pin can be programmed as an input or output pin. address bus ? a16 specifies one of the address lines for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), a16 and emi control signals are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. after reset, the startup state of gpiob0 (gpio or address) is determined as a function of extboot, emi_mode and the flash security setting. see table 4-4 for further information on when this pin is configured as an address pin at reset. in all cases, this state may be changed by writing to gpiob_per. to deactivate the internal pull-up resistor, set bit 0 in the gpiob_pur register. d0 (gpiof9) 59 input/ output input/ output tri-stated input data bus ? d0 - d6 specify part of the data for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), d0 - d6 are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port f gpio ? these seven gpio pins can be individually programmed as input or output pins. at reset, these pins default to the emi data bus function. to deactivate the internal pull-up resistor, set the appropriate gpio bit in the gpiof_pur register. example: gpiof9, set bit 9 in the gpiof_pur register. d1 (gpiof10) 60 d2 (gpiof11) 72 d3 (gpiof12) 75 d4 (gpiof13) 76 d5 (gpiof14) 77 d6 (gpiof15) 78 table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 23 preliminary d7 (gpiof0) 28 input/ output input/ output tri-stated input data bus ? d7 - d14 specify part of the data for external program or data memory accesses. depending upon the state of the drv bit in the emi bus control register (bcr), d7 - d14 are tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. port f gpio ? these eight gpio pins can be individually programmed as input or output pins. at reset, these pins default to data bus functionality. to deactivate the internal pull-up resistor, clear the appropriate gpio bit in the gpiof_pur register. example: gpiof0, clear bit 0 in the gpiof_pur register. d8 (gpiof1) 29 d9 (gpiof2) 30 d10 (gpiof3) 32 d11 (gpiof4) 133 d12 (gpiof5) 134 d13 (gpiof6) 135 d14 (gpiof7) 136 d15 (gpiof8) 137 input/ output input/ output tri-stated input data bus ? d15 specifies part of the data for external program or data memory accesses. most designs will want to change the drv state to drv = 1 instead of using the default setting. port f gpio ? this gpio pin can be individually programmed as an input or output pin. at reset, this pin defaults to the data bus function. to deactivate the internal pull-up resistor, set bit 8 in the gpiof_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 24 freescale semiconductor preliminary rd 45 output tri-stated read enable ? rd is asserted during external memory read cycles. when rd is asserted low, pins d0 - d15 become inputs and an external device is enabled onto the data bus. when rd is deasserted high, the external data is latched inside the device. when rd is asserted, it qualifies the a0 - a16, ps , ds , and csn pins. rd can be connected directly to the oe pin of a static ram or rom. depending upon the state of the drv bit in the emi bus control register (bcr), rd is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. to deactivate the internal pull-up resistor, set the ctrl bit in the sim_pudr register. wr 44 output tri-stated write enable ? wr is asserted during external memory write cycles. when wr is asserted low, pins d0 - d15 become outputs and the device puts data on the bus. when wr is deasserted high, the external data is latched inside the external device. when wr is asserted, it qualifies the a0 - a16, ps , ds, and csn pins. wr can be connected directly to the we pin of a static ram. depending upon the state of the drv bit in the emi bus control register (bcr), wr is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. to deactivate the internal pull-up resistor, set the ctrl bit in the sim_pudr register. ps (cs0 ) (gpiod8) 46 output input/ output tri-stated input program memory select ? this signal is actually cs0 in the emi, which is programmed at reset for compatibility with the 56f80x ps signal. ps is asserted low for external program memory access. depending upon the state of the drv bit in the emi bus control register (bcr), ps is tri-stated when the external bus is inactive. cs0 resets to provide the ps function as defined on the 56f80x devices. port d gpio ? this gpio pin can be individually programmed as an input or output pin. to deactivate the internal pull-up resistor, clear bit 8 in the gpiod_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 25 preliminary ds (cs1 ) (gpiod9) 47 output input/ output tri-stated input data memory select ? this signal is actually cs1 in the emi, which is programmed at reset for compatibility with the 56f80x ds signal. ds is asserted low for external data memory access. depending upon the state of the drv bit in the emi bus control register (bcr), ds is tri-stated when the external bus is inactive. cs1 resets to provide the ds function as defined on the 56f80x devices. port d gpio ? this gpio pin can be individually programmed as an input or output pin. to deactivate the internal pull-up resistor, clear bit 9 in the gpiod_pur register. gpiod0 (cs2 ) ( can2_tx ) 48 input/ output output open drain output input tri-stated output port d gpio ? this gpio pin can be individually programmed as an input or output pin. chip select ? cs2 may be programmed within the emi module to act as a chip select for specific areas of the external memory map. depending upon the state of the drv bit in the emi bus control register (bcr), cs2 is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. flexcan2 transmit data ? can output. at reset, this pin is configured as gpio. this configuration can be changed by setting bit 0 in the gpio_d_per register. then change bit 4 in the sim_gps register to select the desired peripheral function. to deactivate the internal pull-up resistor, clear bit 0 in the gpiod_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 26 freescale semiconductor preliminary gpiod1 (cs3 ) ( can2_rx ) 49 schmitt input/ output output schmitt input input tri-stated input port d gpio ? this gpio pin can be individually programmed as an input or output pin. chip select ? cs3 may be programmed within the emi module to act as a chip select for specific areas of the external memory map. depending upon the state of the drv bit in the emi bus control register (bcr), cs3 is tri-stated when the external bus is inactive. most designs will want to change the drv state to drv = 1 instead of using the default setting. flexcan2 receive data ? this is the can input. this pin has an internal pull-up resistor. at reset, this pin is configured as gpio. this configuration can be changed by setting bit 1 in the gpio_d_per register. then change bit 5 in the sim_gps register to select the desired peripheral function. to deactivate the internal pull-up resistor, clear bit 1 in the gpiod_pur register. txd0 (gpioe0) 4output input/ output tri-stated input transmit data ? sci0 transmit data output port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci output. to deactivate the internal pull-up resistor, clear bit 0 in the gpioe_pur register. rxd0 (gpioe1) 5 input input/ output input input receive data ? sci0 receive data input port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci output. to deactivate the internal pull-up resistor, clear bit 1 in the gpioe_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 27 preliminary txd1 (gpiod6) 42 output input/ output tri-stated input transmit data ? sci1 transmit data output port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci output. to deactivate the internal pull-up resistor, clear bit 6 in the gpiod_pur register. rxd1 (gpiod7) 43 input input/ output input input receive data ? sci1 receive data input port d gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sci input. to deactivate the internal pull-up resistor, clear bit 7 in the gpiod_pur register. tck 121 schmitt input input, pulled low internally test clock input ? this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/eonce port. the pin is connected internally to a pull-down resistor. tms 122 schmitt input input, pulled high internally test mode select input ? this input pin is used to sequence the jtag tap controller?s state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. tdi 123 schmitt input input, pulled high internally test data input ? this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. tdo 124 output tri-stated test data output ? this tri-stateable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 28 freescale semiconductor preliminary trst 120 schmitt input input, pulled high internally test reset ? as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment when a hardware device reset is required and the jtag/eonce module must not be reset. in this case, assert reset , but do not assert trst . to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. phasea0 (ta0) (gpioc4) 139 schmitt input schmitt input/ output schmitt input/ output input input input phase a ? quadrature decoder 0, phasea input ta0 ? timer a, channel 0 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is phasea0. to deactivate the internal pull-up resistor, clear bit 4 of the gpioc_pur register. phaseb0 (ta1) (gpioc5) 140 schmitt input schmitt input/ output schmitt input/ output input input input phase b ? quadrature decoder 0, phaseb input ta1 ? timer a, channel port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is phaseb0. to deactivate the internal pull-up resistor, clear bit 5 of the gpioc_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 29 preliminary index0 (ta2) (gpopc6) 141 schmitt input schmitt input/ output schmitt input/ output input input input index ? quadrature decoder 0, index input ta2 ? timer a, channel 2 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is index0. to deactivate the internal pull-up resistor, clear bit 6 of the gpioc_pur register. home0 (ta3) (gpioc7) 142 schmitt input schmitt input/ output schmitt input/ output input input input home ? quadrature decoder 0, home input ta3 ? timer a, channel 3 port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is home0. to deactivate the internal pull-up resistor, clear bit 7 of the gpioc_pur register. sclk0 (gpioe4) 130 schmitt input/ output schmitt input/ output input input spi 0 serial clock ? in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sclk0. to deactivate the internal pull-up resistor, clear bit 4 in the gpioe_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 30 freescale semiconductor preliminary mosi0 (gpioe5) 132 input/ output input/ output tri-stated input spi 0 master out/slave in ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge the slave device uses to latch the data. port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is mosi0. to deactivate the internal pull-up resistor, clear bit 5 in the gpioe_pur register. miso0 (gpioe6) 131 input/ output input/ output input input spi 0 master in/slave out ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. port e gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is miso0. to deactivate the internal pull-up resistor, clear bit 6 in the gpioe_pur register. ss0 (gpioe7) 129 input input/ output input input spi 0 slave selec t ? ss0 is used in slave mode to indicate to the spi module that the current transfer is to be received. port e gpio ? this gpio pin can be individually programmed as input or output pin. after reset, the default state is ss0 . to deactivate the internal pull-up resistor, clear bit 7 in the gpioe_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 31 preliminary phasea1 (tb0) (sclk1) (gpioc0) 6schmitt input schmitt input/ output schmitt input/ output schmitt input/ output input input input input phase a1 ? quadrature decoder 1, phasea input for decoder 1. tb0 ? timer b, channel 0 spi 1 serial clock ? in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. to activate the spi function, set the phsa_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. in the 56f8366, the default state after reset is phasea1. in the 56f8166, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 0 in the gpioc_pur register. phaseb1 (tb1) (mosi1) (gpioc1) 7schmitt input schmitt input/ output schmitt input/ output schmitt input/ output input input tri-stated input phase b1 ? quadrature decoder 1, phaseb input for decoder 1. tb1 ? timer b, channel 1 spi 1 master out/slave in ? this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge the slave device uses to latch the data. to activate the spi function, set the phsb_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. in the 56f8366, the default state after reset is phaseb1. in the 56f8166, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 1 in the gpioc_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 32 freescale semiconductor preliminary index1 (tb2) (miso1) (gpioc2) 8schmitt input schmitt input/ output schmitt input/ output schmitt input/ output input input input input index1 ? quadrature decoder 1, index input tb2 ? timer b, channel 2 spi 1 master in/slave out ? this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. to activate the spi function, set the index_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as an input or output pin. after reset, the default state is index1. to deactivate the internal pull-up resistor, clear bit 2 in the gpioc_pur register. home1 (tb3) (ss1 ) (gpioc3) 9schmitt input schmitt input/ output schmitt input schmitt input/ output input input input input home ? quadrature decoder 1, home input tb3 ? timer b, channel 3 spi 1 slave select ? in the master mode, this pin is used to arbitrate multiple masters. in slave mode, this pin is used to select the slave. to activate the spi function, set the home_alt bit in the sim_gps register. for details, see part 6.5.8 . port c gpio ? this gpio pin can be individually programmed as input or an output pin. in the 56f8366, the default state after reset is home1. in the 56f8166, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear bit 3 in the gpioc_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 33 preliminary pwma0 62 output tri-state pwma0 - 5 ? these are six pwma outputs. pwma1 64 pwma2 65 pwma3 67 pwma4 68 pwma5 70 isa0 (gpioc8) 113 schmitt input schmitt input/ output input input isa0 - 2 ? these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwma. port c gpio ? these three gpio pins can be individually programmed as input or output pins. in the 56f8366, these pins default to isa functionality after reset. in the 56f8166, the default state is not one of the functions offered and must be reconfigured. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpioc_pur register. for details, see part 6.5.8 . isa1 (gpioc9) 114 isa2 (gpioc10) 115 faulta0 71 schmitt input input faulta0 - 2 ? these three fault input pins are used for disabling selected pwma outputs in cases where fault conditions originate off-chip. to deactivate the internal pull-up resistor, set the pwma0 bit in the sim_pudr register. for details, see part 6.5.8 . faulta1 73 faulta2 74 pwmb0 34 output tri-state pwmb0 - 5 ? six pwmb output pins. pwmb1 35 pwmb2 36 pwmb3 39 pwmb4 40 pwmb5 41 table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 34 freescale semiconductor preliminary isb0 (gpiod10) 50 schmitt input schmitt input/ output input input isb0 - 2 ? these three input current status pins are used for top/bottom pulse width correction in complementary channel operation for pwmb. port d gpio ? these gpio pins can be individually programmed as input or output pins. at reset, these pins default to isb functionality. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpiod_pur register. for details, see part 6.5.8 . isb1 (gpiod11) 52 isb2 (gpiod12) 53 faultb0 56 schmitt input input faultb0 - 3 ? these four fault input pins are used for disabling selected pwmb outputs in cases where fault conditions originate off-chip. to deactivate the internal pull-up resistor, set the pwmb bit in the sim_pudr register. for details, see part 6.5.8 . faultb1 57 faultb2 58 faultb3 61 ana0 88 input input ana0 - 3 ? analog inputs to adc a, channel 0 ana1 89 ana2 90 ana3 91 ana4 92 input input ana4 - 7 ? analog inputs to adc a, channel 1 ana5 93 ana6 94 ana7 95 v refh 101 input input v refh ? analog reference voltage high. v refh must be less than or equal to v dda_adc. v refp 100 input/ output input/ output v refp , v refmid & v refn ? internal pins for voltage reference which are brought off-chip so they can be bypassed. connect to a 0.1 f or low esr capacitor. v refmid 99 v refn 98 v reflo 97 input input v reflo ? analog reference voltage low. this should normally be connected to a low-noise v ssa . table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 35 preliminary anb0 104 input input anb0 - 3 ? analog inputs to adc b, channel 0 anb1 105 anb2 106 anb3 107 anb4 108 input input anb4 - 7 ? analog inputs to adc b, channel 1 anb5 109 anb6 110 anb7 111 temp_sense 96 output output temperature sense diode ? this signal connects to an on-chip diode that can be connected to one of the adc inputs and used to monitor the temperature of the die. must be bypassed with a 0.01 f capacitor. can_rx 127 schmitt input input flexcan receive data ? this is the can input. this pin has an internal pull-up resistor. to deactivate the internal pull-up resistor, set the can bit in the sim_pudr register. can_tx 126 open drain output open drain output flexcan transmit data ? can output tc0 (gpioe8) 118 schmitt input/ output schmitt input/ outpu input input tc0 ? timer c, channel 0 port e gpio ? these gpio pin can be individually programmed as an input or output pin. at reset, this pin defaults to timer functionality. to deactivate the internal pull-up resistor, clear bit 8 of the gpioe_pur register. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 36 freescale semiconductor preliminary td0 (gpioe10) 116 schmitt input/ output schmitt input/ output input input td0 - td1 ? timer d, channels 0 and 1 port e gpio ? these gpio pins can be individually programmed as input or output pins. at reset, these pins default to timer functionality. to deactivate the internal pull-up resistor, clear the appropriate bit of the gpioe_pur register. see part 6.5.6 for details. td1 (gpioe11) 117 irqa 54 schmitt input input external interrupt request a and b ? the irqa and irqb inputs are asynchronous external interrupt requests during stop and wait mode operation. during other operating modes, they are synchronized external interrupt requests, which indicate an external device is requesting service. they can be programmed to be level-sensitive or negative-edge triggered. to deactivate the internal pull-up resistor, set the irq bit in the sim_pudr register. see part 6.5.6 for details. irqb 55 reset 86 schmitt input input reset ? this input is a direct hardware reset on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. when the reset pin is deasserted, the initial chip operating mode is latched from the extboot pin. the internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and the jtag/eonce module must not be reset. in this case, assert reset but do not assert trst . note: the internal power-on reset will assert on initial power-up. to deactivate the internal pull-up resistor, set the reset bit in the sim_pudr register. see part 6.5.6 for details. rsto 85 output output reset output ? this output reflects the internal reset state of the chip. table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8366 technical data, rev. 2.0 freescale semiconductor 37 preliminary extboot 112 schmitt input input external boot ? this input is tied to v dd to force the device to boot from off-chip memory (assuming that the on-chip flash memory is not in a secure state). otherwise, it is tied to ground. for details, see table 4-4 . note: when this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the xboot bit of the sim_pudr; see part 6.5.6 . emi_mode 143 schmitt input input external memory mode ? the emi_mode input is internally tied low (to v ss ). this device will boot from internal flash memory under normal operation. this function is also affected by extboot and the flash security mode. for details, see table 4-4 . if a 20-bit address bus is not desired, then this pin is tied to ground. note: when this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the emi_mode bit of the sim_pudr; see part 6.5.6 . table 2-2 signal and package information for the 144-pin lqfp signal name pin no. type state during reset signal description
56f8366 technical data, rev. 2.0 38 freescale semiconductor preliminary part 3 on-chip clock synthesis (occs) 3.1 introduction refer to the occs chapter of the 56f8300 peripheral user manual for a full description of the occs. the material contained here identifies the specific features of the occs design. figure 3-1 shows the specific occs block diagram to refe rence in the occs chapter in the 56f8300 peripheral user manual . figure 3-1 occs block diagram 3.2 external clock operation the system clock can be derived from an external crys tal, ceramic resonator, or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the extal and xtal pins. 3.2.1 crystal oscillator the internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 10-15 . a recommended crystal oscillator circuit is shown in figure 3-2 . follow the crystal supplier?s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. mux extal xtal feedback lck prescaler clk postscaler clk f out/2 crystal osc loss of reference clock detector lock detector zsrc bus interface & control f out f ref plldb pllcod pllcid bus interface loss of reference clock interrupt sys_clk2 source to sim mux clkmode 2 prescaler ( 1,2,4,8 ) postscaler ( 1,2,4,8 ) mstr_osc pll x (1 to 128)
external clock operation 56f8366 technical data, rev. 2.0 freescale semiconductor 39 preliminary the crystal and associated components should be m ounted as near as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. figure 3-2 connecting to a crystal oscillator note: the occs_cohl bit must be set to 1 when a crystal oscillator is used. the reset condition on the occs_cohl bit is 0. please see the cohl bit in the oscillator control (osctl) register, discussed in the 56f8300 peripheral user manual . 3.2.2 ceramic resonator (default) it is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. a typical ceramic resonator circuit is shown in figure 3-3 . refer to the supplier?s recommendations when select ing a ceramic resonator and associated components. the resonator and components should be mounted as near as possible to the extal and xtal pins. figure 3-3 connecting a ceramic resonator note: the occs_cohl bit must be set to 0 when a ceramic resonator is used. the reset condition on the occs_cohl bit is 0. please see the cohl bit in the oscillator control (osctl) register, discussed in the 56f8300 peripheral user manual . sample external crystal parameters: r z = 750 k ? note: if the operating temperature range is limited to below 85 o c (105 o c junction), then r z = 10 meg ? clkmode = 0 extal xtal r z cl1 cl2 crystal frequency = 4 - 8mhz (optimized for 8mhz) extal xtal r z extal xtal r z sample external ceramic resonator parameters: r z = 750 k ? extal xtal r z c1 cl1 cl2 c2 resonator frequency = 4 - 8mhz (optimized for 8mhz) 3 terminal 2 terminal clkmode = 0
56f8366 technical data, rev. 2.0 40 freescale semiconductor preliminary 3.2.3 external clock source the recommended method of connecting an external clock is given in figure 3-4 . the external clock source is connected to xtal and the extal pi n is grounded. set occs_cohl bit high when using an external clock source as well. figure 3-4 connecting an external clock register 3.3 registers when referring to the register definitions for the occs in the 56f8300 peripheral user manual , use the register definitions without the internal relaxation oscillator, since the 56f8366/56f8166 devices do not contain this oscillator. part 4 memory map 4.1 introduction the 56f8366 and 56f8166 devices are 16-bit motor-control chip based on the 56800e core. these parts use a harvard-style architecture with two indepe ndent memory spaces for data and program. on-chip ram and flash memories are used in both spaces. this section provides memory maps for: ? program address space, including the interrupt vector table ? data address space, including the eonce memory and peripheral memory maps on-chip memory sizes for each device are summarized in table 4-1 . flash memories? restrictions are identified in the ?use restrictions? column of table 4-1 . xtal extal external v ss clock note: when using an external clocking source with this configuration, the input ?clkmode? should be high and the cohl bit in the osctl register should be set to 1.
program map 56f8366 technical data, rev. 2.0 freescale semiconductor 41 preliminary note: data flash and program ram are not available on the 56f8166 device. 4.2 program map the operating mode control bits (ma and mb) in the operating mode register (omr) control the program memory map. at reset, these bits are set as indicated in table 4-2 . table 4-4 shows the memory map configurations that are possible at reset. after reset, the omr ma bit can be changed and will have an effect on the p-space memory map, as shown in table 4-3 . changing the omr mb bit will have no effect. table 4-1 chip memory configurations on-chip memory 56f8366 56f8166 use restrictions program flash 512kb 512kb erase / program via flash interface unit and word writes to cdbw data flash 32kb ? erase / program via flash interface unit and word writes to cdbw. data flash can be read via either cdbr or xdb2, but not by both simultaneously program ram 4kb ? none data ram 32kb 32kb none program boot flash 32kb 32kb erase / program via flash interface unit and word to cdbw table 4-2 omr mb/ma value at reset omr mb = flash secured state 1, 2 1. this bit is only configured at reset. if the flash secured state changes, this will not be reflected in mb until the next res et. 2. changing mb in software will not affect flash memory security. omr ma = extboot pin chip operating mode 0 0 mode 0 ? internal boot; emi is configured to use 16 address lines; flash memory is secured; external p-space is not allowed; the eonce is disabled 0 1 not valid; cannot boot externally if the flash is secured and will actually configure to 00 state 1 0 mode 0 ? internal boot; emi is configured to use 16 address lines 1 1 mode 1 ? external boot; flash memory is not secured; emi configuration is determined by the state of the emi_mode pin
56f8366 technical data, rev. 2.0 42 freescale semiconductor preliminary the device?s external memory interface (emi) can ope rate much like the 56f80x family?s emi, or it can be operated in a mode similar to that used on other products in the 56800e family. initially, cs0 and cs1 are configured as ps and ds , in a mode compatible with earlier 56800 devices. eighteen address lines are required to shadow the first 192k of internal program space when booting externally for development purposes. therefore, th e entire complement of on-chip memory cannot be accessed using a 16-bit 56800-compatible address bus. to address this situation, the emi_mode pin can be used to configure four gpio pi ns as address[19:16] upon reset (only one of these pins [a16] is usable in the 56f8366/56f8166). the emi_mode pin also affects the reset vector address, as provided in table 4-4 . additional pins must be configured as address or chip select signals to access addresses at p:$10 and above. table 4-3 changing omr ma value during normal operation omr ma chip operating mode 0 use internal p-space memory map configuration 1 use external p-space memory map configuration ? if mb = 0 at reset, changing this bit has no effect.
program map 56f8366 technical data, rev. 2.0 freescale semiconductor 43 preliminary note: program ram is not available on the 56f8166 device. table 4-4 program memory map at reset begin/end address mode 0 (ma = 0) mode 1 1 (ma = 1) 1. if flash security mode is enabled, extboot mode 1 cannot be used. see security features, part 7 . internal boot external boot internal boot 16-bit external address bus emi_mode = 0 2 , 3 16-bit external address bus 2. this mode provides maximum compatibility with 56f80x parts while operating externally. 3. ?emi_mode =0? when emi_mode pin is tied to ground at boot up. emi_mode = 1 4 20-bit external address bus 4. ?emi_mode =1? when emi_mode pin is tied to v dd at boot up. p:$1f ffff p:$10 0000 external program memory 5 5. not accessible in reset configuration, since the address is above p:$00 ffff. the higher bit address/gpio (and/or chip se- lects) pins must be reconfigured before this external memory is accessible. external program memory 5 external program memory 6 6. not accessible in reset configuration, since the address is above p:$0f ffff. the higher bit address/gpio (and/or chip se- lects) pins must be reconfigured before this external memory is accessible. p:$0f ffff p:$05 0000 external program memory cop reset address = 04 0002 7 boot location = 04 0000 7 7. booting from this external address allows prototyping of the internal boot flash. p:$04 ffff p:$04 f800 on-chip program ram 4kb p:$04 f7ff p:$04 4000 reserved 92kb p:$04 3fff p:$04 0000 boot flash 32kb cop reset address = 04 0002 boot location = 04 0000 boot flash 32kb (not used for boot in this mode) p:$03 ffff p:$02 0000 internal program flash 8 256kb internal program flash 256kb p:$01 ffff p:$01 0000 internal program flash 8 256kb 8. two independent program flash blocks allow one to be programmed/erased while executing from another. each block must have its own mass erase. internal program flash 128kb p:$00 ffff p:$00 0000 external program memory cop reset address = 00 0002 boot location = 00 0000
56f8366 technical data, rev. 2.0 44 freescale semiconductor preliminary 4.3 interrupt vector table table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. the table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. the priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. all level 3 inte rrupts will be serviced before level 2, and so on. for a selected priority level, the lowest vector number has the highest priority. the location of the vector table is determined by th e vector base address (vba) register. please see part 5.6.12 for the reset value of the vba. in some configurations, the reset address and cop reset a ddress will correspond to vector 0 and 1 of the interrupt vector table. in these instances, the first tw o locations in the vector table must contain branch or jmp instructions. all other entries must contain jsr instructions. note: pwma, flexcan, quadrature decoder 1, and quad timers b and d are not available on the 56f8166 device. table 4-5 interrupt vector table contents 1 peripheral vector number priority level vector base address + interrupt function reserved for reset overlay 2 reserved for cop reset overlay 2 core 2 3 p:$04 illegal instruction core 3 3 p:$06 sw interrupt 3 core 4 3 p:$08 hw stack overflow core 5 3 p:$0a misaligned long word access core 6 1-3 p:$0c once step counter core 7 1-3 p:$0e once breakpoint unit 0 reserved core 9 1-3 p:$12 once trace buffer core 10 1-3 p:$14 once transmit register empty core 11 1-3 p:$16 once receive register full reserved core 14 2 p:$1c sw interrupt 2 core 15 1 p:$1e sw interrupt 1 core 16 0 p:$20 sw interrupt 0 core 17 0-2 p:$22 irqa core 18 0-2 p:$24 irqb
interrupt vector table 56f8366 technical data, rev. 2.0 freescale semiconductor 45 preliminary reserved lvi 20 0-2 p:$28 low-voltage detector (power sense) pll 21 0-2 p:$2a pll fm 22 0-2 p:$2c fm access error interrupt fm 23 0-2 p:$2e fm command complete fm 24 0-2 p:$30 fm command, data and address buffers empty reserved flexcan 26 0-2 p:$34 flexcan bus off flexcan 27 0-2 p:$36 flexcan error flexcan 28 0-2 p:$38 flexcan wake up flexcan 29 0-2 p:$3a flexcan message buffer interrupt gpiof 30 0-2 p:$3c gpio f gpioe 31 0-2 p:$3e gpio e gpiod 32 0-2 p:$40 gpio d gpioc 33 0-2 p:$42 gpio c gpiob 34 0-2 p:$44 gpio b gpioa 35 0-2 p:$46 gpio a reserved spi1 38 0-2 p:$4c spi 1 receiver full spi1 39 0-2 p:$4e spi 1 transmitter empty spi0 40 0-2 p:$50 spi 0 receiver full spi0 41 0-2 p:$52 spi 0 transmitter empty sci1 42 0-2 p:$54 sci 1 transmitter empty sci1 43 0-2 p:$56 sci 1 transmitter idle reserved sci1 45 0-2 p:$5a sci 1 receiver error sci1 46 0-2 p:$5c sci 1 receiver full dec1 47 0-2 p:$5e quadrature decoder #1 home switch or watchdog dec1 48 0-2 p:$60 quadrature decoder #1 index pulse dec0 49 0-2 p:$62 quadrature decoder #0 home switch or watchdog dec0 50 0-2 p:$64 quadrature decoder #0 index pulse reserved table 4-5 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
56f8366 technical data, rev. 2.0 46 freescale semiconductor preliminary tmrd 52 0-2 p:$68 timer d, channel 0 tmrd 53 0-2 p:$6a timer d, channel 1 tmrd 54 0-2 p:$6c timer d, channel 2 tmrd 55 0-2 p:$6e timer d, channel 3 tmrc 56 0-2 p:$70 timer c, channel 0 tmrc 57 0-2 p:$72 timer c, channel 1 tmrc 58 0-2 p:$74 timer c, channel 2 tmrc 59 0-2 p:$76 timer c, channel 3 tmrb 60 0-2 p:$78 timer b, channel 0 tmrb 61 0-2 p:$7a timer b, channel 1 tmrb 62 0-2 p:$7c timer b, channel 2 tmrb 63 0-2 p:$7e timer b, channel 3 tmra 64 0-2 p:$80 timer a, channel 0 tmra 65 0-2 p:$82 timer a, channel 1 tmra 66 0-2 p:$84 timer a, channel 2 tmra 67 0-2 p:$86 timer a, channel 3 sci0 68 0-2 p:$88 sci 0 transmitter empty sci0 69 0-2 p:$8a sci 0 transmitter idle reserved sci0 71 0-2 p:$8e sci 0 receiver error sci0 72 0-2 p:$90 sci 0 receiver full adcb 73 0-2 p:$92 adc b conversion compete / end of scan adca 74 0-2 p:$94 adc a conversion complete / end of scan adcb 75 0-2 p:$96 adc b zero crossing or limit error adca 76 0-2 p:$98 adc a zero crossing or limit error pwmb 77 0-2 p:$9a reload pwm b pwma 78 0-2 p:$9c reload pwm a pwmb 79 0-2 p:$9e pwm b fault pwma 80 0-2 p:$a0 pwm a fault core 81 - 1 p:$a2 sw interrupt lp flexcan2 82 0-2 p:$a4 flexcan bus off table 4-5 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
data map 56f8366 technical data, rev. 2.0 freescale semiconductor 47 preliminary 4.4 data map note: data flash is not available on the 56f8166 device. flexcan2 83 0-2 p:$a6 flexcan error flexcan2 84 0-2 p:$a8 flexcan wake up flexcan2 85 0-2 p:$aa flexcan message buffer interrupt 1. two words are allocated for each entry in the vector table. this does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. if the vba is set to $0200 (or vba = 0000 for mode 1, emi_ mode = 0), the first two locati ons of the vect or table are the chip reset addresses; therefore, these locations are not interrupt vectors. 2. table 4-6 data memory map 1 1. all addresses are 16-bit word addresses, not byte addresses. begin/end address ex = 0 2 2. in the operation mode register (omr). ex = 1 x:$ff ffff x:$ff ff00 eonce 256 locations allocated eonce 256 locations allocated x:$ff feff x:$01 0000 external memory external memory x:$00 ffff x:$00 f000 on-chip peripherals 4096 locations allocated on-chip peripherals 4096 locations allocated x:$00 efff x:$00 8000 external memory external memory x:$00 7fff x:$00 4000 on-chip data flash 32kb x:$00 3fff x:$00 0000 on-chip data ram 32kb 3 3. the data ram is organized as an 8k x 32-bit memory to allow single-cycle long-word operations. table 4-5 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
56f8366 technical data, rev. 2.0 48 freescale semiconductor preliminary 4.5 flash memory map figure 4-1 illustrates the flash memory (fm) map on the system bus. the flash memory is divided into three functional blocks. the program and boot memories reside on the program memory buses. they are controlled by one set of banked registers. data memory flash resides on the data memory buses and is controlled se parately by its own se t of banked registers. the top nine words of the program memory flash are treated as special memory locations. the content of these words is used to control the operation of the fl ash controller. because these words are part of the flash memory content, their state is maintained during power-down and reset. during chip initialization, the content of these memory locations is loaded into flash memory control registers, detailed in the flash memory chapter of the 56f8300 peripheral user manual . these configuration parameters are located between $03_fff7 and $03_ffff. figure 4-1 flash array memory maps data memory data_flash_start + $3fff data_flash_start + $0000 fm_base + $14 fm_base + $00 boot_flash_start + $3fff boot_flash_start = $04_0000 fm_prog_mem_top = $01_ffff block 0 odd (2 bytes) $00_0003 block 0 even (2 bytes) $00_0002 block 0 odd (2 bytes) $00_0001 block 0 even (2 bytes) $00_0000 block 1 odd (2 bytes) $02_0003 block 1 even (2 bytes) $02_0002 block 1 odd (2 bytes) $02_0001 block 1 even (2 bytes) $02_0000 program memory 32kb boot 256kb program configure field 256kb program banked registers unbanked registers 32kb prog_flash_start + $03_ffff prog_flash_start + $02_0000 prog_flash_start + $01_ffff prog_flash_start = $00_0000 note: data flash is not available in the 56f8166 device.
eonce memory map 56f8366 technical data, rev. 2.0 freescale semiconductor 49 preliminary table 4-7 shows the page and sector sizes used within each flash memory block on the chip. note: data flash is not available on the 56f8166 device. please see 56f8300 peripheral user manual for additional flash information. 4.6 eonce memory map table 4-7. flash memory partitions flash size sectors sector size page size program flash 512kb 16 16k x 16 bits 1024 x 16 bits data flash 32kb 16 1024 x 16 bits 256 x 16 bits boot flash 32kb 4 4k x 16 bits 512 x 16 bits table 4-8 eonce memory map address register acronym register name reserved x:$ff ff8a oescr external signal control register reserved x:$ff ff8e obcntr breakpoint unit [0] counter reserved x:$ff ff90 obmsk (32 bits) breakpoint 1 unit [0] mask register x:$ff ff91 ? breakpoint 1 unit [0] mask register x:$ff ff92 obar2 (32 bits) breakpoint 2 unit [0] address register x:$ff ff93 ? breakpoint 2 unit [0] address register x:$ff ff94 obar1 (24 bits) breakpoint 1 unit [0] address register x:$ff ff95 ? breakpoint 1 unit [0] address register x:$ff ff96 obcr (24 bits) breakpoint unit [0] control register x:$ff ff97 ? breakpoint unit [0] control register x:$ff ff98 otb (21-24 bits/stage) trace buffer register stages x:$ff ff99 ? trace buffer register stages x:$ff ff9a otbpr (8 bits) trace buffer pointer register x:$ff ff9b otbcr trace buffer control register x:$ff ff9c obase (8 bits) peripheral base address register x:$ff ff9d osr status register
56f8366 technical data, rev. 2.0 50 freescale semiconductor preliminary 4.7 peripheral memory mapped registers on-chip peripheral registers are part of the data memory map on the 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read/written using word accesses only. table 4-9 summarizes base addresses for the set of peripherals on the 56f8366 and 56f8166 devices. peripherals are listed in or der of the base address. the following tables list all of the peripheral registers require d to control or access the peripherals. note: features in italics are not available on the 56f8166 device. x:$ff ff9e oscntr (24 bits) instruction step counter x:$ff ff9f ? instruction step counter x:$ff ffa0 ocr (bits) control register reserved x:$ff fffc oclsr (8 bits) core lock / unlock status register x:$ff fffd otxrxsr (8 bits) transmit and receive status and control register x:$ff fffe otx / orx (32 bits) transmit register / receive register x:$ff ffff otx1 / orx1 transmit register upper word receive register upper word table 4-9 data memory peripheral base address map summary peripheral prefix base address table number external memory interface emi x:$00 f020 4-10 timer a tmra x:$00 f040 4-11 timer b tmrb x:$00 f080 4-12 timer c tmrc x:$00 f0c0 4-13 timer d tmrd x:$00 f100 4-14 pwm a pwma x:$00 f140 4-15 pwm b pwmb x:$00 f160 4-16 quadrature decoder 0 dec0 x:$00 f180 4-17 quadrature decoder 1 dec1 x:$00 f190 4-18 itcn itcn x:$00 f1a0 4-19 adc a adca x:$00 f200 4-20 table 4-8 eonce memory map (continued) address register acronym register name
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 51 preliminary adc b adcb x:$00 f240 4-21 temperature sensor tsensor x:$00 f270 4-22 sci #0 sci0 x:$00 f280 4-23 sci #1 sci1 x:$00 f290 4-24 spi #0 spi0 x:$00 f2a0 4-25 spi #1 spi1 x:$00 f2b0 4-26 cop cop x:$00 f2c0 4-27 pll, osc clkgen x:$00 f2d0 4-28 gpio port a gpioa x:$00 f2e0 4-29 gpio port b gpiob x:$00 f300 4-30 gpio port c gpioc x:$00 f310 4-31 gpio port d gpiod x:$00 f320 4-32 gpio port e gpioe x:$00 f330 4-33 gpio port f gpiof x:$00 f340 4-34 sim sim x:$00 f350 4-35 power supervisor lvi x:$00 f360 4-36 fm fm x:$00 f400 4-37 flexcan fc x:$00 f800 4-38 flexcan2 fc x:$00 fa00 4-39 table 4-9 data memory peripheral ba se address map summary (continued) peripheral prefix base address table number
56f8366 technical data, rev. 2.0 52 freescale semiconductor preliminary table 4-10 external memory integration registers address map (emi_base = $00 f020) register acronym address offset register description reset value csbar 0 $0 chip select base address register 0 0x0004 = 64k when extboot = 0 or emi_mode = 0 0x0008 = 1m when emi_mode = 1 (selects entire program space for cs0) note that a17-a19 are not available in this package csbar 1 $1 chip select base address register 1 0x0004 = 64k when emi_mode = 0 0x0008 = 1m when emi_mode = 1 (selects a0 - a19 addressable data space for cs1) note that a17-a19 are not available in this package csbar 2 $2 chip select base address register 2 csbar 3 $3 chip select base address register 3 csbar 4 $4 chip select base address register 4 csbar 5 $5 chip select base address register 5 csbar 6 $6 chip select base address register 6 csbar 7 $7 chip select base address register 7 csor 0 $8 chip select option register 0 0x5fcb programmed for chip select for program space, word wide, read and write, 11 waits csor 1 $9 chip select option register 1 0x5fab programmed for chip select for data space, word wide, read and write, 11 waits csor 2 $a chip select option register 2 csor 3 $b chip select option register 3 csor 4 $c chip select option register 4 csor 5 $d chip select option register 5 csor 6 $e chip select option register 6
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 53 preliminary csor 7 $f chip select option register 7 cstc 0 $10 chip select timing control register 0 cstc 1 $11 chip select timing control register 1 cstc 2 $12 chip select timing control register 2 cstc 3 $13 chip select timing control register 3 cstc 4 $14 chip select timing control register 4 cstc 5 $15 chip select timing control register 5 cstc 6 $16 chip select timing control register 6 cstc 7 $17 chip select timing control register 7 bcr $18 bus control register 0x016b sets the default number of wait states to 11 for both read and write accesses table 4-11 quad timer a registers address map (tmra_base = $00 f040) register acronym address offset register description tmra0_cmp1 $0 compare register 1 tmra0_cmp2 $1 compare register 2 tmra0_cap $2 capture register tmra0_load $3 load register tmra0_hold $4 hold register tmra0_cntr $5 counter register tmra0_ctrl $6 control register tmra0_scr $7 status and control register tmra0_cmpld1 $8 comparator load register 1 tmra0_cmpld2 $9 comparator load register 2 tmra0_comscr $a comparator status and control register reserve tmra1_cmp1 $10 compare register 1 tmra1_cmp2 $11 compare register 2 tmra1_cap $12 capture register tmra1_load $13 load register tmra1_hold $14 hold register table 4-10 external memory integrat ion registers address map (continued) (emi_base = $00 f020) register acronym address offset register description reset value
56f8366 technical data, rev. 2.0 54 freescale semiconductor preliminary tmra1_cntr $15 counter register tmra1_ctrl $16 control register tmra1_scr $17 status and control register tmra1_cmpld1 $18 comparator load register 1 tmra1_cmpld2 $19 comparator load register 2 tmra1_comscr $1a comparator status and control register reserved tmra2_cmp1 $20 compare register 1 tmra2_cmp2 $21 compare register 2 tmra2_cap $22 capture register tmra2_load $23 load register tmra2_hold $24 hold register tmra2_cntr $25 counter register tmra2_ctrl $26 control register tmra2_scr $27 status and control register tmra2_cmpld1 $28 comparator load register 1 tmra2_cmpld2 $29 comparator load register 2 tmra2_comscr $2a comparator status and control register reserved tmra3_cmp1 $30 compare register 1 tmra3_cmp2 $31 compare register 2 tmra3_cap $32 capture register tmra3_load $33 load register tmra3_hold $34 hold register tmra3_cntr $35 counter register tmra3_ctrl $36 control register tmra3_scr $37 status and control register tmra3_cmpld1 $38 comparator load register 1 tmra3_cmpld2 $39 comparator load register 2 tmra3_comsc $3a comparator status and control register table 4-11 quad timer a regi sters address map (continued) (tmra_base = $00 f040) register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 55 preliminary table 4-12 quad timer b registers address map (tmrb_base = $00 f080) quad timer b is not available in the 56f8166 device register acronym address offset register description tmrb0_cmp1 $0 compare register 1 tmrb0_cmp2 $1 compare register 2 tmrb0_cap $2 capture register tmrb0_load $3 load register tmrb0_hold $4 hold register tmrb0_cntr $5 counter register tmrb0_ctrl $6 control register tmrb0_scr $7 status and control register tmrb0_cmpld1 $8 comparator load register 1 tmrb0_cmpld2 $9 comparator load register 2 tmrb0_comscr $a comparator status and control register reserved tmrb1_cmp1 $10 compare register 1 tmrb1_cmp2 $11 compare register 2 tmrb1_cap $12 capture register tmrb1_load $13 load register tmrb1_hold $14 hold register tmrb1_cntr $15 counter register tmrb1_ctrl $16 control register tmrb1_scr $17 status and control register tmrb1_cmpld1 $18 comparator load register 1 tmrb1_cmpld2 $19 comparator load register 2 tmrb1_comscr $1a comparator status and control register reserved tmrb2_cmp1 $20 compare register 1 tmrb2_cmp2 $21 compare register 2 tmrb2_cap $22 capture register tmrb2_load $23 load register tmrb2_hold $24 hold register tmrb2_cntr $25 counter register
56f8366 technical data, rev. 2.0 56 freescale semiconductor preliminary tmrb2_ctrl $26 control register tmrb2_scr $27 status and control register tmrb2_cmpld1 $28 comparator load register 1 tmrb2_cmpld2 $29 comparator load register 2 tmrb2_comscr $2a comparator status and control register reserved tmrb3_cmp1 $30 compare register 1 tmrb3_cmp2 $31 compare register 2 tmrb3_cap $32 capture register tmrb3_load $33 load register tmrb3_hold $34 hold register tmrb3_cntr $35 counter register tmrb3_ctrl $36 control register tmrb3_scr $37 status and control register tmrb3_cmpld1 $38 comparator load register 1 tmrb3_cmpld2 $39 comparator load register 2 tmrb3_comscr $3a comparator status and control register table 4-13 quad timer c registers address map (tmrc_base = $00 f0c0) register acronym address offset register description tmrc0_cmp1 $0 compare register 1 tmrc0_cmp2 $1 compare register 2 tmrc0_cap $2 capture register tmrc0_load $3 load register tmrc0_hold $4 hold register tmrc0_cntr $5 counter register tmrc0_ctrl $6 control register tmrc0_scr $7 status and control register tmrc0_cmpld1 $8 comparator load register 1 tmrc0_cmpld2 $9 comparator load register 2 table 4-12 quad timer b regi sters address map (continued) (tmrb_base = $00 f080) quad timer b is not available in the 56f8166 device register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 57 preliminary tmrc0_comscr $a comparator status and control register reserved tmrc1_cmp1 $10 compare register 1 tmrc1_cmp2 $11 compare register 2 tmrc1_cap $12 capture register tmrc1_load $13 load register tmrc1_hold $14 hold register tmrc1_cntr $15 counter register tmrc1_ctrl $16 control register tmrc1_scr $17 status and control register tmrc1_cmpld1 $18 comparator load register 1 tmrc1_cmpld2 $19 comparator load register 2 tmrc1_comscr $1a comparator status and control register reserved tmrc2_cmp1 $20 compare register 1 tmrc2_cmp2 $21 compare register 2 tmrc2_cap $22 capture register tmrc2_load $23 load register tmrc2_hold $24 hold register tmrc2_cntr $25 counter register tmrc2_ctrl $26 control register tmrc2_scr $27 status and control register tmrc2_cmpld1 $28 comparator load register 1 tmrc2_cmpld2 $29 comparator load register 2 tmrc2_comscr $2a comparator status and control register reserved tmrc3_cmp1 $30 compare register 1 tmrc3_cmp2 $31 compare register 2 tmrc3_cap $32 capture register tmrc3_load $33 load register tmrc3_hold $34 hold register tmrc3_cntr $35 counter register table 4-13 quad timer c regi sters address map (continued) (tmrc_base = $00 f0c0) register acronym address offset register description
56f8366 technical data, rev. 2.0 58 freescale semiconductor preliminary tmrc3_ctrl $36 control register tmrc3_scr $37 status and control register tmrc3_cmpld1 $38 comparator load register 1 tmrc3_cmpld2 $39 comparator load register 2 tmrc3_comscr $3a comparator status and control register table 4-14 quad timer d registers address map (tmrd_base = $00 f100) quad timer d is not available in the 56f8166 device register acronym address offset register description tmrd0_cmp1 $0 compare register 1 tmrd0_cmp2 $1 compare register 2 tmrd0_cap $2 capture register tmrd0_load $3 load register tmrd0_hold $4 hold register tmrd0_cntr $5 counter register tmrd0_ctrl $6 control register tmrd0_scr $7 status and control register tmrd0_cmpld1 $8 comparator load register 1 tmrd0_cmpld2 $9 comparator load register 2 tmrd0_comscr $a comparator status and control register reserved tmrd1_cmp1 $10 compare register 1 tmrd1_cmp2 $11 compare register 2 tmrd1_cap $12 capture register tmrd1_load $13 load register tmrd1_hold $14 hold register tmrd1_cntr $15 counter register tmrd1_ctrl $16 control register tmrd1_scr $17 status and control register tmrd1_cmpld1 $18 comparator load register 1 tmrd1_cmpld2 $19 comparator load register 2 table 4-13 quad timer c regi sters address map (continued) (tmrc_base = $00 f0c0) register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 59 preliminary tmrd1_comscr $1a comparator status and control register reserved tmrd2_cmp1 $20 compare register 1 tmrd2_cmp2 $21 compare register 2 tmrd2_cap $22 capture register tmrd2_load $23 load register tmrd2_hold $24 hold register tmrd2_cntr $25 counter register tmrd2_ctrl $26 control register tmrd2_scr $27 status and control register tmrd2_cmpld1 $28 comparator load register 1 tmrd2_cmpld2 $29 comparator load register 2 tmrd2_comscr $2a comparator status and control register reserved tmrd3_cmp1 $30 compare register 1 tmrd3_cmp2 $31 compare register 2 tmrd3_cap $32 capture register tmrd3_load $33 load register tmrd3_hold $34 hold register tmrd3_cntr $35 counter register tmrd3_ctrl $36 control register tmrd3_scr $37 status and control register tmrd3_cmpld1 $38 comparator load register 1 tmrd3_cmpld2 $39 comparator load register 2 tmrd3_comscr $3a comparator status and control register table 4-14 quad timer d regi sters address map (continued) (tmrd_base = $00 f100) quad timer d is not available in the 56f8166 device register acronym address offset register description
56f8366 technical data, rev. 2.0 60 freescale semiconductor preliminary table 4-15 pulse width modulator a registers address map (pwma_base = $00 f140) pwma is not available in the 56f8166 device register acronym address offset register description pwma_pmctl $0 control register pwma_pmfctl $1 fault control register pwma_pmfsa $2 fault status acknowledge register pwma_pmout $3 output control register pwma_pmcnt $4 counter register pwma_pwmcm $5 counter modulo register pwma_pwmval0 $6 value register 0 pwma_pwmval1 $7 value register 1 pwma_pwmval2 $8 value register 2 pwma_pwmval3 $9 value register 3 pwma_pwmval4 $a value register 4 pwma_pwmval5 $b value register 5 pwma_pmdeadtm $c dead time register pwma_pmdismap1 $d disable mapping register 1 pwma_pmdismap2 $e disable mapping register 2 pwma_pmcfg $f configure register pwma_pmccr $10 channel control register pwma_pmport $11 port register pwma_pmiccr $12 pwm internal correction control register table 4-16 pulse width modulator b registers address map (pwmb_base = $00 f160) register acronym address offset register description pwmb_pmctl $0 control register pwmb_pmfctl $1 fault control register pwmb_pmfsa $2 fault status acknowledge register pwmb_pmout $3 output control register pwmb_pmcnt $4 counter register pwmb_pwmcm $5 counter modulo register pwmb_pwmval0 $6 value register 0
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 61 preliminary pwmb_pwmval1 $7 value register 1 pwmb_pwmval2 $8 value register 2 pwmb_pwmval3 $9 value register 3 pwmb_pwmval4 $a value register 4 pwmb_pwmval5 $b value register 5 pwmb_pmdeadtm $c dead time register pwmb_pmdismap1 $d disable mapping register 1 pwmb_pmdismap2 $e disable mapping register 2 pwmb_pmcfg $f configure register pwmb_pmccr $10 channel control register pwmb_pmport $11 port register pwmb_pmiccr $12 pwm internal correction control register table 4-17 quadrature decoder 0 registers address map (dec0_base = $00 f180) register acronym address offset register description dec0_deccr $0 decoder control register dec0_fir $1 filter interval register dec0_wtr $2 watchdog time-out register dec0_posd $3 position difference counter register dec0_posdh $4 position difference counter hold register dec0_rev $5 revolution counter register dec0_revh $6 revolution hold register dec0_upos $7 upper position counter register dec0_lpos $8 lower position counter register dec0_uposh $9 upper position hold register dec0_lposh $a lower position hold register dec0_uir $b upper initialization register dec0_lir $c lower initialization register dec0_imr $d input monitor register table 4-16 pulse width modulator b registers address map (continued) (pwmb_base = $00 f160) register acronym address offset register description
56f8366 technical data, rev. 2.0 62 freescale semiconductor preliminary table 4-18 quadrature decoder 1 registers address map (dec1_base = $00 f190) quadrature decoder 1 is not available on the 56f8166 device register acronym address offset register description dec1_deccr $0 decoder control register dec1_fir $1 filter interval register dec1_wtr $2 watchdog time-out register dec1_posd $3 position difference counter register dec1_posdh $4 position difference counter hold register dec1_rev $5 revolution counter register dec1_revh $6 revolution hold register dec1_upos $7 upper position counter register dec1_lpos $8 lower position counter register dec1_uposh $9 upper position hold register dec1_lposh $a lower position hold register dec1_uir $b upper initialization register dec1_lir $c lower initialization register dec1_imr $d input monitor register table 4-19 interrupt control registers address map (itcn_base = $00 f1a0) register acronym address offset register description ipr 0 $0 interrupt priority register 0 ipr 1 $1 interrupt priority register 1 ipr 2 $2 interrupt priority register 2 ipr 3 $3 interrupt priority register 3 ipr 4 $4 interrupt priority register 4 ipr 5 $5 interrupt priority register 5 ipr 6 $6 interrupt priority register 6 ipr 7 $7 interrupt priority register 7 ipr 8 $8 interrupt priority register 8 ipr 9 $9 interrupt priority register 9 vba $a vector base address register fim0 $b fast interrupt match register 0
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 63 preliminary fival0 $c fast interrupt vector address low 0 register fivah0 $d fast interrupt vector address high 0 register fim1 $e fast interrupt match register 1 fival1 $f fast interrupt vector address low 1 register fivah1 $10 fast interrupt vector address high 1 register irqp 0 $11 irq pending register 0 irqp 1 $12 irq pending register 1 irqp 2 $13 irq pending register 2 irqp 3 $14 irq pending register 3 irqp 4 $15 irq pending register 4 irqp 5 $16 irq pending register 5 reserved ictl $1d interrupt control register reserved ipr10 $1f interrupt priority register 10 table 4-20 analog-to-digital converter registers address map (adca_base = $00 f200) register acronym address offset register description adca_cr 1 $0 control register 1 adca_cr 2 $1 control register 2 adca_zcc $2 zero crossing control register adca_lst 1 $3 channel list register 1 adca_lst 2 $4 channel list register 2 adca_sdis $5 sample disable register adca_stat $6 status register adca_lstat $7 limit status register adca_zcstat $8 zero crossing status register adca_rslt 0 $9 result register 0 adca_rslt 1 $a result register 1 adca_rslt 2 $b result register 2 adca_rslt 3 $c result register 3 table 4-19 interrupt control registers address map (continued) (itcn_base = $00 f1a0) register acronym address offset register description
56f8366 technical data, rev. 2.0 64 freescale semiconductor preliminary adca_rslt 4 $d result register 4 adca_rslt 5 $e result register 5 adca_rslt 6 $f result register 6 adca_rslt 7 $10 result register 7 adca_llmt 0 $11 low limit register 0 adca_llmt 1 $12 low limit register 1 adca_llmt 2 $13 low limit register 2 adca_llmt 3 $14 low limit register 3 adca_llmt 4 $15 low limit register 4 adca_llmt 5 $16 low limit register 5 adca_llmt 6 $17 low limit register 6 adca_llmt 7 $18 low limit register 7 adca_hlmt 0 $19 high limit register 0 adca_hlmt 1 $1a high limit register 1 adca_hlmt 2 $1b high limit register 2 adca_hlmt 3 $1c high limit register 3 adca_hlmt 4 $1d high limit register 4 adca_hlmt 5 $1e high limit register 5 adca_hlmt 6 $1f high limit register 6 adca_hlmt 7 $20 high limit register 7 adca_ofs 0 $21 offset register 0 adca_ofs 1 $22 offset register 1 adca_ofs 2 $23 offset register 2 adca_ofs 3 $24 offset register 3 adca_ofs 4 $25 offset register 4 adca_ofs 5 $26 offset register 5 adca_ofs 6 $27 offset register 6 adca_ofs 7 $28 offset register 7 adca_power $29 power control register adca_cal $2a adc calibration register table 4-20 analog-to-digital converte r registers address map (continued) (adca_base = $00 f200) register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 65 preliminary table 4-21 analog-to-digital converter registers address map (adcb_base = $00 f240) register acronym address offset register description adcb_cr 1 $0 control register 1 adcb_cr 2 $1 control register 2 adcb_zcc $2 zero crossing control register adcb_lst 1 $3 channel list register 1 adcb_lst 2 $4 channel list register 2 adcb_sdis $5 sample disable register adcb_stat $6 status register adcb_lstat $7 limit status register adcb_zcstat $8 zero crossing status register adcb_rslt 0 $9 result register 0 adcb_rslt 1 $a result register 1 adcb_rslt 2 $b result register 2 adcb_rslt 3 $c result register 3 adcb_rslt 4 $d result register 4 adcb_rslt 5 $e result register 5 adcb_rslt 6 $f result register 6 adcb_rslt 7 $10 result register 7 adcb_llmt 0 $11 low limit register 0 adcb_llmt 1 $12 low limit register 1 adcb_llmt 2 $13 low limit register 2 adcb_llmt 3 $14 low limit register 3 adcb_llmt 4 $15 low limit register 4 adcb_llmt 5 $16 low limit register 5 adcb_llmt 6 $17 low limit register 6 adcb_llmt 7 $18 low limit register 7 adcb_hlmt 0 $19 high limit register 0 adcb_hlmt 1 $1a high limit register 1 adcb_hlmt 2 $1b high limit register 2 adcb_hlmt 3 $1c high limit register 3 adcb_hlmt 4 $1d high limit register 4 adcb_hlmt 5 $1e high limit register 5
56f8366 technical data, rev. 2.0 66 freescale semiconductor preliminary adcb_hlmt 6 $1f high limit register 6 adcb_hlmt 7 $20 high limit register 7 adcb_ofs 0 $21 offset register 0 adcb_ofs 1 $22 offset register 1 adcb_ofs 2 $23 offset register 2 adcb_ofs 3 $24 offset register 3 adcb_ofs 4 $25 offset register 4 adcb_ofs 5 $26 offset register 5 adcb_ofs 6 $27 offset register 6 adcb_ofs 7 $28 offset register 7 adcb_power $29 power control register adcb_cal $2a adc calibration register table 4-22 temperature sensor register address map (tsensor_base = $00 f270) temperature sensor is not available in the 56f8166 device register acronym address offset register description tsensor_cntl $0 control register table 4-23 serial communication interface 0 registers address map (sci0_base = $00 f280) register acronym address offset register description sci0_scibr $0 baud rate register sci0_scicr $1 control register reserved sci0_scisr $3 status register sci0_scidr $4 data register table 4-21 analog-to-digital converter registers address map (adcb_base = $00 f240) (continued) register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 67 preliminary table 4-24 serial communication interface 1 registers address map (sci1_base = $00 f290) register acronym address offset register description sci1_scibr $0 baud rate register sci1_scicr $1 control register reserved sci1_scisr $3 status register sci1_scidr $4 data register table 4-25 serial peripheral interface 0 registers address map (spi0_base = $00 f2a0) register acronym address offset register description spi0_spscr $0 status and control register spi0_spdsr $1 data size register spi0_spdrr $2 data receive register spi0_spdtr $3 data transmitter register table 4-26 serial peripheral interface 1 registers address map (spi1_base = $00 f2b0) register acronym address offset register description spi1_spscr $0 status and control register spi1_spdsr $1 data size register spi1_spdrr $2 data receive register spi1_spdtr $3 data transmitter register table 4-27 computer operating properly registers address map (cop_base = $00 f2c0) register acronym address offset register description copctl $0 control register copto $1 time out register copctr $2 counter register
56f8366 technical data, rev. 2.0 68 freescale semiconductor preliminary table 4-28 clock generation m odule registers address map (clkgen_base = $00 f2d0) register acronym address offset register description pllcr $0 control register plldb $1 divide-by register pllsr $2 status register reserved shutdown $4 shutdown register osctl $5 oscillator control register table 4-29 gpioa registers address map (gpioa_base = $00 f2e0) register acronym address offset register description reset value gpioa_pur $0 pull-up enable register 0 x 3fff gpioa_dr $1 data register 0 x 0000 gpioa_ddr $2 data direction register 0 x 0000 gpioa_per $3 peripheral enable register 0 x 3fff gpioa_iar $4 interrupt assert register 0 x 0000 gpioa_ienr $5 interrupt enable register 0 x 0000 gpioa_ipolr $6 interrupt polarity register 0 x 0000 gpioa_ipr $7 interrupt pending register 0 x 0000 gpioa_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioa_ppmode $9 push-pull mode register 0 x 3fff gpioa_rawdata $a raw data input register ?
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 69 preliminary table 4-30 gpiob registers address map (gpiob_base = $00 f300) register acronym address offset register description reset value gpiob_pur $0 pull-up enable register 0 x 00ff gpiob_dr $1 data register 0 x 0000 gpiob_ddr $2 data direction register 0 x 0000 gpiob_per $3 peripheral enable register 0 x 000f for 20-bit emi address at reset. 0 x 0000 for all other cases. see table 4-4 for details. gpiob_iar $4 interrupt assert register 0 x 0000 gpiob_ienr $5 interrupt enable register 0 x 0000 gpiob_ipolr $6 interrupt polarity register 0 x 0000 gpiob_ipr $7 interrupt pending register 0 x 0000 gpiob_iesr $8 interrupt edge-sensitive register 0 x 0000 gpiob_ppmode $9 push-pull mode register 0 x 00ff gpiob_rawdata $a raw data input register ? table 4-31 gpioc registers address map (gpioc_base = $00 f310) register acronym address offset register description reset value gpioc_pur $0 pull-up enable register 0 x 07ff gpioc_dr $1 data register 0 x 0000 gpioc_ddr $2 data direction register 0 x 0000 gpioc_per $3 peripheral enable register 0 x 07ff gpioc_iar $4 interrupt assert register 0 x 0000 gpioc_ienr $5 interrupt enable register 0 x 0000 gpioc_ipolr $6 interrupt polarity register 0 x 0000 gpioc_ipr $7 interrupt pending register 0 x 0000 gpioc_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioc_ppmode $9 push-pull mode register 0 x 07ff gpioc_rawdata $a raw data input register ?
56f8366 technical data, rev. 2.0 70 freescale semiconductor preliminary table 4-32 gpiod registers address map (gpiod_base = $00 f320) register acronym address offset register description reset value gpiod_pur $0 pull-up enable register 0 x 1fff gpiod_dr $1 data register 0 x 0000 gpiod_ddr $2 data direction register 0 x 0000 gpiod_per $3 peripheral enable register 0 x 1fc0 gpiod_iar $4 interrupt assert register 0 x 0000 gpiod_ienr $5 interrupt enable register 0 x 0000 gpiod_ipolr $6 interrupt polarity register 0 x 0000 gpiod_ipr $7 interrupt pending register 0 x 0000 gpiod_iesr $8 interrupt edge-sensitive register 0 x 0000 gpiod_ppmode $9 push-pull mode register 0 x 1fff gpiod_rawdata $a raw data input register ? table 4-33 gpioe registers address map (gpioe_base = $00 f330) register acronym address offset register description reset value gpioe_pur $0 pull-up enable register 0 x 3fff gpioe_dr $1 data register 0 x 0000 gpioe_ddr $2 data direction register 0 x 0000 gpioe_per $3 peripheral enable register 0 x 3fff gpioe_iar $4 interrupt assert register 0 x 0000 gpioe_ienr $5 interrupt enable register 0 x 0000 gpioe_ipolr $6 interrupt polarity register 0 x 0000 gpioe_ipr $7 interrupt pending register 0 x 0000 gpioe_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioe_ppmode $9 push-pull mode register 0 x 3fff gpioe_rawdata $a raw data input register ?
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 71 preliminary table 4-34 gpiof registers address map (gpiof_base = $00 f340) register acronym address offset register description reset value gpiof_pur $0 pull-up enable register 0 x ffff gpiof_dr $1 data register 0 x 0000 gpiof_ddr $2 data direction register 0 x 0000 gpiof_per $3 peripheral enable register 0 x ffff gpiof_iar $4 interrupt assert register 0 x 0000 gpiof_ienr $5 interrupt enable register 0 x 0000 gpiof_ipolr $6 interrupt polarity register 0 x 0000 gpiof_ipr $7 interrupt pending register 0 x 0000 gpiof_iesr $8 interrupt edge-sensitive register 0 x 0000 gpiof_ppmode $9 push-pull mode register 0 x ffff gpiof_rawdata $a raw data input register ? table 4-35 system integration module registers address map (sim_base = $00 f350) register acronym address offset register description sim_control $0 control register sim_rststs $1 reset status register sim_scr0 $2 software control register 0 sim_scr1 $3 software control register 1 sim_scr2 $4 software control register 2 sim_scr3 $5 software control register 3 sim_msh_id $6 most significant half jtag id sim_lsh_id $7 least significant half jtag id sim_pudr $8 pull-up disable register reserved sim_clkosr $a clock out select register sim_gps $b quad decoder 1 / timer b / spi 1 select register sim_pce $c peripheral clock enable register sim_isalh $d i/o short address location high register sim_isall $e i/o short address location low register sim_pce2 $f peripheral clock enable register 2
56f8366 technical data, rev. 2.0 72 freescale semiconductor preliminary table 4-36 power supervisor registers address map (lvi_base = $00 f360) register acronym address offset register description lvi_control $0 control register lvi_status $1 status register table 4-37 flash module registers address map (fm_base = $00 f400) register acronym address offset register description fmclkd $0 clock divider register fmmcr $1 module control register reserved fmsech $3 security high half register fmsecl $4 security low half register reserved reserved fmprot $10 protection register (banked) fmprotb $11 protection boot register (banked) reserved fmustat $13 user status register (banked) fmcmd $14 command register (banked) reserved reserved fmopt 0 $1a 16-bit information option register 0 hot temperature adc reading of temperature sensor; value set during factory test fmopt 1 $1b 16-bit information option register 1 not used fmopt 2 $1c 16-bit information option register 2 room temperature adc reading of temperature sensor; value set during factory test
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 73 preliminary table 4-38 flexcan registers address map (fc_base = $00 f800) flexcan is not available in the 56f8166 device register acronym address offset register description fcmcr $0 module configuration register reserved fcctl0 $3 control register 0 register fcctl1 $4 control register 1 register fctmr $5 free-running timer register fcmaxmb $6 maximum message buffer configuration register reserved fcrxgmask_h $8 receive global mask high register fcrxgmask_l $9 receive global mask low register fcrx14mask_h $a receive buffer 14 mask high register fcrx14mask_l $b receive buffer 14 mask low register fcrx15mask_h $c receive buffer 15 mask high register fcrx15mask_l $d receive buffer 15 mask low register reserved fcstatus $10 error and status register fcimask1 $11 interrupt masks 1 register fciflag1 $12 interrupt flags 1 register fcr/t_error_cntrs $13 receive and transmit error counters register reserved reserved reserved fcmb0_control $40 message buffer 0 control / status register fcmb0_id_high $41 message buffer 0 id high register fcmb0_id_low $42 message buffer 0 id low register fcmb0_data $43 message buffer 0 data register fcmb0_data $44 message buffer 0 data register fcmb0_data $45 message buffer 0 data register fcmb0_data $46 message buffer 0 data register reserved fcmsb1_control $48 message buffer 1 control / status register
56f8366 technical data, rev. 2.0 74 freescale semiconductor preliminary fcmsb1_id_high $49 message buffer 1 id high register fcmsb1_id_low $4a message buffer 1 id low register fcmb1_data $4b message buffer 1 data register fcmb1_data $4c message buffer 1 data register fcmb1_data $4d message buffer 1 data register fcmb1_data $4e message buffer 1 data register reserved fcmb2_control $50 message buffer 2 control / status register fcmb2_id_high $51 message buffer 2 id high register fcmb2_id_low $52 message buffer 2 id low register fcmb2_data $53 message buffer 2 data register fcmb2_data $54 message buffer 2 data register fcmb2_data $55 message buffer 2 data register fcmb2_data $56 message buffer 2 data register reserved fcmb3_control $58 message buffer 3 control / status register fcmb3_id_high $59 message buffer 3 id high register fcmb3_id_low $5a message buffer 3 id low register fcmb3_data $5b message buffer 3 data register fcmb3_data $5c message buffer 3 data register fcmb3_data $5d message buffer 3 data register fcmb3_data $5e message buffer 3 data register reserved fcmb4_control $60 message buffer 4 control / status register fcmb4_id_high $61 message buffer 4 id high register fcmb4_id_low $62 message buffer 4 id low register fcmb4_data $63 message buffer 4 data register fcmb4_data $64 message buffer 4 data register fcmb4_data $65 message buffer 4 data register fcmb4_data $66 message buffer 4 data register reserved table 4-38 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56f8166 device register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 75 preliminary fcmb5_control $68 message buffer 5 control / status register fcmb5_id_high $69 message buffer 5 id high register fcmb5_id_low $6a message buffer 5 id low register fcmb5_data $6b message buffer 5 data register fcmb5_data $6c message buffer 5 data register fcmb5_data $6d message buffer 5 data register fcmb5_data $6e message buffer 5 data register reserved fcmb6_control $70 message buffer 6 control / status register fcmb6_id_high $71 message buffer 6 id high register fcmb6_id_low $72 message buffer 6 id low register fcmb6_data $73 message buffer 6 data register fcmb6_data $74 message buffer 6 data register fcmb6_data $75 message buffer 6 data register fcmb6_data $76 message buffer 6 data register reserved fcmb7_control $78 message buffer 7 control / status register fcmb7_id_high $79 message buffer 7 id high register fcmb7_id_low $7a message buffer 7 id low register fcmb7_data $7b message buffer 7 data register fcmb7_data $7c message buffer 7 data register fcmb7_data $7d message buffer 7 data register fcmb7_data $7e message buffer 7 data register reserved fcmb8_control $80 message buffer 8 control / status register fcmb8_id_high $81 message buffer 8 id high register fcmb8_id_low $82 message buffer 8 id low register fcmb8_data $83 message buffer 8 data register fcmb8_data $84 message buffer 8 data register fcmb8_data $85 message buffer 8 data register fcmb8_data $86 message buffer 8 data register table 4-38 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56f8166 device register acronym address offset register description
56f8366 technical data, rev. 2.0 76 freescale semiconductor preliminary reserved fcmb9_control $88 message buffer 9 control / status register fcmb9_id_high $89 message buffer 9 id high register fcmb9_id_low $8a message buffer 9 id low register fcmb9_data $8b message buffer 9 data register fcmb9_data $8c message buffer 9 data register fcmb9_data $8d message buffer 9 data register fcmb9_data $8e message buffer 9 data register reserved fcmb10_control $90 message buffer 10 control / status register fcmb10_id_high $91 message buffer 10 id high register fcmb10_id_low $92 message buffer 10 id low register fcmb10_data $93 message buffer 10 data register fcmb10_data $94 message buffer 10 data register fcmb10_data $95 message buffer 10 data register fcmb10_data $96 message buffer 10 data register reserved fcmb11_control $98 message buffer 11 control / status register fcmb11_id_high $99 message buffer 11 id high register fcmb11_id_low $9a message buffer 11 id low register fcmb11_data $9b message buffer 11 data register fcmb11_data $9c message buffer 11 data register fcmb11_data $9d message buffer 11 data register fcmb11_data $9e message buffer 11 data register reserved fcmb12_control $a0 message buffer 12 control / status register fcmb12_id_high $a1 message buffer 12 id high register fcmb12_id_low $a2 message buffer 12 id low register fcmb12_data $a3 message buffer 12 data register fcmb12_data $a4 message buffer 12 data register fcmb12_data $a5 message buffer 12 data register table 4-38 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56f8166 device register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 77 preliminary fcmb12_data $a6 message buffer 12 data register reserved fcmb13_control $a8 message buffer 13 control / status register fcmb13_id_high $a9 message buffer 13 id high register fcmb13_id_low $aa message buffer 13 id low register fcmb13_data $ab message buffer 13 data register fcmb13_data $ac message buffer 13 data register fcmb13_data $ad message buffer 13 data register fcmb13_data $ae message buffer 13 data register reserved fcmb14_control $b0 message buffer 14 control / status register fcmb14_id_high $b1 message buffer 14 id high register fcmb14_id_low $b2 message buffer 14 id low register fcmb14_data $b3 message buffer 14 data register fcmb14_data $b4 message buffer 14 data register fcmb14_data $b5 message buffer 14 data register fcmb14_data $b6 message buffer 14 data register reserved fcmb15_control $b8 message buffer 15 control / status register fcmb15_id_high $b9 message buffer 15 id high register fcmb15_id_low $ba message buffer 15 id low register fcmb15_data $bb message buffer 15 data register fcmb15_data $bc message buffer 15 data register fcmb15_data $bd message buffer 15 data register fcmb15_data $be message buffer 15 data register reserved table 4-38 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56f8166 device register acronym address offset register description
56f8366 technical data, rev. 2.0 78 freescale semiconductor preliminary table 4-39 flexcan2 registers address map (fc2_base = $00 fa00) flexcan2 is not available in the 56f8166 device register acronym address offset register description fc2mcr $0 module configuration register reserved fc2ctl0 $3 control register 0 register fc2ctl1 $4 control register 1 register fc2tmr $5 free-running timer register fc2maxmb $6 maximum message buffer configuration register fc2imask2 $7 interrupt masks 2 register fc2rxgmask_h $8 receive global mask high register fc2rxgmask_l $9 receive global mask low register fc2rx14mask_h $a receive buffer 14 mask high register fc2rx14mask_l $b receive buffer 14 mask low register fc2rx15mask_h $c receive buffer 15 mask high register fc2rx15mask_l $d receive buffer 15 mask low register reserved fc2status $10 error and status register fc2imask1 $11 interrupt masks 1 register fc2iflag1 $12 interrupt flags 1 register fc2r/t_error_cntrs $13 receive and transmit error counters register reserved fc2iflag 2 $1b interrupt flags 2 register reserved fc2mb0_control $40 message buffer 0 control / status register fc2mb0_id_high $41 message buffer 0 id high register fc2mb0_id_low $42 message buffer 0 id low register fc2mb0_data $43 message buffer 0 data register fc2mb0_data $44 message buffer 0 data register fc2mb0_data $45 message buffer 0 data register fc2mb0_data $46 message buffer 0 data register reserved fc2msb1_control $48 message buffer 1 control / status register
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 79 preliminary fc2msb1_id_high $49 message buffer 1 id high register fc2msb1_id_low $4a message buffer 1 id low register fc2mb1_data $4b message buffer 1 data register fc2mb1_data $4c message buffer 1 data register fc2mb1_data $4d message buffer 1 data register fc2mb1_data $4e message buffer 1 data register reserved fc2mb2_control $50 message buffer 2 control / status register fc2mb2_id_high $51 message buffer 2 id high register fc2mb2_id_low $52 message buffer 2 id low register fc2mb2_data $53 message buffer 2 data register fc2mb2_data $54 message buffer 2 data register fc2mb2_data $55 message buffer 2 data register fc2mb2_data $56 message buffer 2 data register reserved fc2mb3_control $58 message buffer 3 control / status register fc2mb3_id_high $59 message buffer 3 id high register fc2mb3_id_low $5a message buffer 3 id low register fc2mb3_data $5b message buffer 3 data register fc2mb3_data $5c message buffer 3 data register fc2mb3_data $5d message buffer 3 data register fc2mb3_data $5e message buffer 3 data register reserved fc2mb4_control $60 message buffer 4 control / status register fc2mb4_id_high $61 message buffer 4 id high register fc2mb4_id_low $62 message buffer 4 id low register fc2mb4_data $63 message buffer 4 data register fc2mb4_data $64 message buffer 4 data register fc2mb4_data $65 message buffer 4 data register fc2mb4_data $66 message buffer 4 data register reserved table 4-39 flexcan2 registers address map (continued) (fc2_base = $00 fa00) flexcan2 is not available in the 56f8166 device register acronym address offset register description
56f8366 technical data, rev. 2.0 80 freescale semiconductor preliminary fc2mb5_control $68 message buffer 5 control / status register fc2mb5_id_high $69 message buffer 5 id high register fc2mb5_id_low $6a message buffer 5 id low register fc2mb5_data $6b message buffer 5 data register fc2mb5_data $6c message buffer 5 data register fc2mb5_data $6d message buffer 5 data register fc2mb5_data $6e message buffer 5 data register reserved fc2mb6_control $70 message buffer 6 control / status register fc2mb6_id_high $71 message buffer 6 id high register fc2mb6_id_low $72 message buffer 6 id low register fc2mb6_data $73 message buffer 6 data register fc2mb6_data $74 message buffer 6 data register fc2mb6_data $75 message buffer 6 data register fc2mb6_data $76 message buffer 6 data register reserved fc2mb7_control $78 message buffer 7 control / status register fc2mb7_id_high $79 message buffer 7 id high register fc2mb7_id_low $7a message buffer 7 id low register fc2mb7_data $7b message buffer 7 data register fc2mb7_data $7c message buffer 7 data register fc2mb7_data $7d message buffer 7 data register fc2mb7_data $7e message buffer 7 data register reserved fc2mb8_control $80 message buffer 8 contro l /status register fc2mb8_id_high $81 message buffer 8 id high register fc2mb8_id_low $82 message buffer 8 id low register fc2mb8_data $83 message buffer 8 data register fc2mb8_data $84 message buffer 8 data register fc2mb8_data $85 message buffer 8 data register fc2mb8_data $86 message buffer 8 data register table 4-39 flexcan2 registers address map (continued) (fc2_base = $00 fa00) flexcan2 is not available in the 56f8166 device register acronym address offset register description
peripheral memory mapped registers 56f8366 technical data, rev. 2.0 freescale semiconductor 81 preliminary reserved fc2mb9_control $88 message buffer 9 control / status register fc2mb9_id_high $89 message buffer 9 id high register fc2mb9_id_low $8a message buffer 9 id low register fc2mb9_data $8b message buffer 9 data register fc2mb9_data $8c message buffer 9 data register fc2mb9_data $8d message buffer 9 data register fc2mb9_data $8e message buffer 9 data register reserved fc2mb10_control $90 message buffer 10 control / status register fc2mb10_id_high $91 message buffer 10 id high register fc2mb10_id_low $92 message buffer 10 id low register fc2mb10_data $93 message buffer 10 data register fc2mb10_data $94 message buffer 10 data register fc2mb10_data $95 message buffer 10 data register fc2mb10_data $96 message buffer 10 data register reserved fc2mb11_control $98 message buffer 11 control / status register fc2mb11_id_high $99 message buffer 11 id high register fc2mb11_id_low $9a message buffer 11 id low register fc2mb11_data $9b message buffer 11 data register fc2mb11_data $9c message buffer 11 data register fc2mb11_data $9d message buffer 11 data register fc2mb11_data $9e message buffer 11 data register reserved fc2mb12_control $a0 message buffer 12 control / status register fc2mb12_id_high $a1 message buffer 12 id high register fc2mb12_id_low $a2 message buffer 12 id low register fc2mb12_data $a3 message buffer 12 data register fc2mb12_data $a4 message buffer 12 data register table 4-39 flexcan2 registers address map (continued) (fc2_base = $00 fa00) flexcan2 is not available in the 56f8166 device register acronym address offset register description
56f8366 technical data, rev. 2.0 82 freescale semiconductor preliminary fc2mb12_data $a5 message buffer 12 data register fc2mb12_data $a6 message buffer 12 data register reserved fc2mb13_control $a8 message buffer 13 control / status register fc2mb13_id_high $a9 message buffer 13 id high register fc2mb13_id_low $aa message buffer 13 id low register fc2mb13_data $ab message buffer 13 data register fc2mb13_data $ac message buffer 13 data register fc2mb13_data $ad message buffer 13 data register fc2mb13_data $ae message buffer 13 data register reserved fc2mb14_control $b0 message buffer 14 control / status register fc2mb14_id_high $b1 message buffer 14 id high register fc2mb14_id_low $b2 message buffer 14 id low register fc2mb14_data $b3 message buffer 14 data register fc2mb14_data $b4 message buffer 14 data register fc2mb14_data $b5 message buffer 14 data register fc2mb14_data $b6 message buffer 14 data register reserved fc2mb15_control $b8 message buffer 15 control / status register fc2mb15_id_high $b9 message buffer 15 id high register fc2mb15_id_low $ba message buffer 15 id low register fc2mb15_data $bb message buffer 15 data register fc2mb15_data $bc message buffer 15 data register fc2mb15_data $bd message buffer 15 data register fc2mb15_data $be message buffer 15 data register reserved table 4-39 flexcan2 registers address map (continued) (fc2_base = $00 fa00) flexcan2 is not available in the 56f8166 device register acronym address offset register description
factory programmed memory 56f8366 technical data, rev. 2.0 freescale semiconductor 83 preliminary 4.8 factory programmed memory the boot flash memory block is programmed duri ng manufacturing with a default serial bootloader program. the serial bootloader application can be used to load a user application into the program and data flash ( not available in the 56f8166 device ) memories of the device. the 56f83xx sci/can bootloader user manual (mc56f83xxblum) provides detailed information on this firmware. an application note, production flash programming (an1973), details how the serial bootloader program can be used to perform production flash programming of the on board flash memories as well as other potential methods. like all the flash memory blocks the boot flash can be erased and programmed by the user. the serial bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the boot flash memory. part 5 interrupt controller (itcn) 5.1 introduction the interrupt controller (itcn) module is used to arbitrate between various interrupt requests (irqs), to signal to the 56800e core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. 5.2 features the itcn module design includes these distinctive features: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restart clocks out of wait and stop modes ? drives initial address on the address bus after reset for further information, see table 4-5 , interrupt vector table contents. 5.3 functional description the interrupt controller is a slave on the ipbus. it contains registers allowing each of the 86 interrupt sources to be set to one of four priority levels, ex cluding certain interrupts of fixed priority. next, all of the interrupt requests of a given leve l are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. within a given priority level, zero is the highest priority, while number 85 is the lowest. 5.3.1 normal interrupt handling once the itcn has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector addre ss is generated. normal interrupt ha ndling concatenates the vba and the vector number to determine the vector address. in this way, an offset is generated into the vector table for each interrupt.
56f8366 technical data, rev. 2.0 84 freescale semiconductor preliminary 5.3.2 interrupt nesting interrupt exceptions may be nested to allow an irq of higher priority than the current exception to be serviced. the following tables define the ne sting requirements for each priority level. 5.3.3 fast interrupt handling fast interrupts are described in the dsp56800e reference manual . the interrupt controller recognizes fast interrupts before the core does. a fast interrupt is defined (to the itcn) by: 1. setting the priority of the interrupt as level 2, with the appropriate field in the ipr registers 2. setting the fimn register to the appropriate vector number 3. setting the fivaln and fivahn registers with the address of the code for the fast interrupt when an interrupt occurs, its vector number is compar ed with the fim0 and fim1 register values. if a match occurs, and it is a level 2 in terrupt, the itcn handles it as a fast interrupt. the itcn takes the vector address from the appropriate fivaln and fivahn regist ers, instead of generating an address that is an offset from the vba. the core then fetches the instruction from the indicated vector adddress and if it is not a jsr, the core starts its fast interrupt handling. table 5-1 interrupt mask bit definition sr[9] 1 1. core status register bits indicating current interrupt mask within the core. sr[8] 1 permitted exceptions masked exceptions 0 0 priorities 0, 1, 2, 3 none 0 1 priorities 1, 2, 3 priority 0 1 0 priorities 2, 3 priorities 0, 1 1 1 priority 3 priorities 0, 1, 2 table 5-2 interrupt priority encoding ipic_level[1:0] 1 1. see ipic field definition in part 5.6.30.2 . current interrupt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 10 priority 1 priorities 2, 3 11 priorities 2 or 3 priority 3
block diagram 56f8366 technical data, rev. 2.0 freescale semiconductor 85 preliminary 5.4 block diagram figure 5-1 interrupt controller block diagram 5.5 operating modes the itcn module design contains two major modes of operation: ? functional mode the itcn is in this mode by default. ? wait and stop modes during wait and stop modes, the system clocks and the 56800e core are turned off. the itcn will signal a pending irq to the system integration module (sim) to restart the clocks and service the irq. an irq can only wake up the core if the irq is enabled prior to entering the wait or stop mode. also, the irqa and irqb signals automatically become low-level sensitive in these modes even if the control register bits are set to make them falling-edge sensitive. this is because there is no clock available to detect the falling edge. a peripheral which requires a clock to generate interrupts will not be able to generate interrupts during stop mode. the flexcan module can wake the device from stop mode, and a reset will do just that, or irqa and irqb can wake it up. priority level 2 -> 4 decode int1 priority level 2 -> 4 decode int82 level 0 82 -> 7 priority encoder any0 level 3 82 -> 7 priority encoder any3 int vab ipic control 7 7 pic_en iack sr[9:8]
56f8366 technical data, rev. 2.0 86 freescale semiconductor preliminary 5.6 register descriptions a register address is the sum of a base address and an address offset. the base address is defined at the system level and the address offset is defined at th e module level. the itcn peripheral has 24 registers. table 5-3 itcn register summary (itcn_base = $00 f1a0) register acronym base address + register name section location ipr0 $0 interrupt priority register 0 5.6.1 ipr1 $1 interrupt priority register 1 5.6.2 ipr2 $2 interrupt priority register 2 5.6.3 ipr3 $3 interrupt priority register 3 5.6.4 ipr4 $4 interrupt priority register 4 5.6.5 ipr5 $5 interrupt priority register 5 5.6.6 ipr6 $6 interrupt priority register 6 5.6.7 ipr7 $7 interrupt priority register 7 5.6.8 ipr8 $8 interrupt priority register 8 5.6.9 ipr9 $9 interrupt priority register 9 5.6.10 vba $a vector base address register 5.6.11 fim0 $b fast interrupt 0 match register 5.6.12 fival0 $c fast interrupt 0 vector address low register 5.6.13 fivah0 $d fast interrupt 0 vector address high register 5.6.14 fim1 $e fast interrupt 1 match register 5.6.15 fival1 $f fast interrupt 1 vector address low register 5.6.16 fivah1 $10 fast interrupt 1 vector address high register 5.6.17 irqp0 $11 irq pending register 0 5.6.18 irqp1 $12 irq pending register 1 5.6.19 irqp2 $13 irq pending register 2 5.6.20 irqp3 $14 irq pending register 3 5.6.21 irqp4 $15 irq pending register 4 5.6.22 irqp5 $16 irq pending register 5 5.6.23 reserved ictl $1d interrupt control register 5.6.30 reserved ipr10 $1f interrupt priority register 10 5.6.32 note : the ipr10 register is not available in the 56f8166 device.
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 87 preliminary add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 ipr0 r 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 w $1 ipr1 r 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl w $2 ipr2 r fmcbe ipl fmcc ipl fmerr ipl lock ipl lvi ipl 0 0 irqb ipl irqa ipl w $3 ipr3 r gpiod ipl gpioe ipl gpiof ipl fcmsgbuf ipl fcwkup ipl fcerr ipl fcboff ipl 0 0 w $4 ipr4 r spi0_rcv ipl spi1_xmit ipl spi1_rcv ipl 0 0 0 0 gpioa ipl gpiob ipl gpioc ipl w $5 ipr5 r dec1_xirq ipl dec1_hirq ipl sci1_rcv ipl sci1_rerr ipl 0 0 sci1_tidl ipl sci1_xmit ipl spi0_xmit ipl w $6 ipr6 r tmrc0 ipl tmrd3 ipl tmrd2 ipl tmrd1 ipl tmrd0 ipl 0 0 dec0_xirq ipl dec0_hirq ipl w $7 ipr7 r tmra0 ipl tmrb3 ipl tmrb2 ipl tmrb1 ipl tmrb0 ipl tmrc3 ipl tmrc2 ipl tmrc1 ipl w $8 ipr8 r sci0_rcv ipl sci0_rerr ipl 0 0 sci0_tidl ipl sci0_xmit ipl tmra3 ipl tmra2 ipl tmra1 ipl w $9 ipr9 r pwma f ipl pwmb f ipl pwma_rl ipl pwmb_rl ipl adca_zc ipl abcb_zc ipl adca_cc ipl adcb_cc ipl w $a vba r 0 0 0 vector base address w $b fim0 r 0 0 0 0 0 0 0 0 0 fast interrupt 0 w $c fival0 r fast interrupt 0 vector address low w $d fivah0 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high w $e fim1 r 0 0 0 0 0 0 0 0 0 fast interrupt 1 w $f fival1 r fast interrupt 1 vector address low w $10 fivah1 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high w $11 irqp0 r pending [16:2] 1 w $12 irqp1 r pending [32:17] w $13 irqp2 r pending [48:33] w $14 irqp3 r pending [64:49] w $15 irqp4 r pending [80:65] w $16 irqp5 r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 pending [81] w reserved $1d ictl r int ipic vab int_dis 1 irqb state irqa state irqb edg irqa edg w reserved $1f ipr10 r 0 0 0 0 0 0 0 0 flexcan2 msgbuf ipl flexcan2 wkup ipl flexcan2 err ipl flexcan2 boff ipl w = reserved figure 5-2 itcn register map summary
56f8366 technical data, rev. 2.0 88 freescale semiconductor preliminary 5.6.1 interrupt priority register 0 (ipr0) figure 5-3 interrupt priority register 0 (ipr0) 5.6.1.1 reserved?bits 15?14 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.1.2 eonce breakpoint unit 0 interrupt priority level (bkpt_u0 ipl)? bits13?12 this field is used to set the interrupt priority levels for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.3 eonce step counter interrupt priority level (stpcnt ipl)? bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.4 reserved?bits 9?0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.2 interrupt priority register 1 (ipr1) figure 5-4 interrupt priority register 1 (ipr1) base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 write reset 0000000000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl write reset 0000000000000000
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 89 preliminary 5.6.2.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.2.2 eonce receive register full interrupt priority level (rx_reg ipl)?bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.2.3 eonce transmit register empty interrupt priority level (tx_reg ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.2.4 eonce trace buffer interrupt priority level (trbuf ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.3 interrupt priority register 2 (ipr2) figure 5-5 interrupt priority register 2 (ipr2) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fmcbe ipl fmcc ipl fmerr ipl lock ipl lvi ipl 0 0 irqb ipl irqa ipl write reset 0000000000000000
56f8366 technical data, rev. 2.0 90 freescale semiconductor preliminary 5.6.3.1 flash memory command, data, address buffers empty interrupt priority level (fmcbe ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.2 flash memory command complete priority level (fmcc ipl)? bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.3 flash memory error interrupt priority level (fmerr ipl)?bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.4 pll loss of lock interrupt priority level (lock ipl)?bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 91 preliminary 5.6.3.5 low voltage detector interrupt priority level (lvi ipl)?bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.6 reserved?bits 5?4 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.3.7 external irq b interrupt priority level (irqb ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.8 external irq a interrupt priority level (irqa ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4 interrupt priority register 3 (ipr3) figure 5-6 interrupt priority register 3 (ipr3) base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read gpiod ipl gpioe ipl gpiof ipl fcmsgbuf ipl fcwkup ipl fcerr ipl fcboff ipl 0 0 write reset 000000 0 0 0 0 0 0 0 0 0 0
56f8366 technical data, rev. 2.0 92 freescale semiconductor preliminary 5.6.4.1 gpiod interrupt priority level (gpiod ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.2 gpioe interrupt priority level (gpioe ipl)?bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.3 gpiof interrupt priority level (gpiof ipl)?bits 11?10 this field is used to set the interrupt priority le vel for irqs. this irq is limited to priorities 0 through 2two. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.4 flexcan message buffer interrupt priority level (fcmsgbuf ipl)? bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 93 preliminary 5.6.4.5 flexcan wake up interrupt priority level (fcwkup ipl)? bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.6 flexcan error interrupt priority level (fcerr ipl)? bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.7 flexcan bus off interrupt priority level (fcboff ipl)? bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.8 reserved?bits 1?0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.5 interrupt priority register 4 (ipr4) figure 5-7 interrupt priority register 4 (ipr4) base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spi0_rcv ipl spi1_xmit ipl spi1_rcv ipl 0 0 0 0 gpioa ipl gpiob ipl gpioc ipl write reset 0000000000000000
56f8366 technical data, rev. 2.0 94 freescale semiconductor preliminary 5.6.5.1 spi0 receiver full interrupt priority level (spi0_rcv ipl)? bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.2 spi1 transmit empty interrupt priority level (spi1_xmit ipl)? bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.3 spi1 receiver full interrupt priority level (spi1_rcv ipl)? bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.4 reserved?bits 9?6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.5.5 gpioa interrupt priority level (gpioa ipl)?bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 95 preliminary 5.6.5.6 gpiob interrupt priority level (gpiob ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.7 gpioc interrupt priority level (gpioc ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6 interrupt priority register 5 (ipr5) figure 5-8 interrupt priority register 5 (ipr5) 5.6.6.1 quadrature decoder 1 index pulse interrupt priority level (dec1_xirq ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read dec1_xirq ipl dec1_hirq ipl sci1_rcv ipl sci1_rerr ipl 0 0 sci1_tidl ipl sci1_xmit ipl spi0_xmit ipl write reset 000000 0 0 00000000
56f8366 technical data, rev. 2.0 96 freescale semiconductor preliminary 5.6.6.2 quadrature decoder 1 home signal transition or watchdog timer interrupt priority level (dec1_hirq ipl)?bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.3 sci 1 receiver full interrupt priority level (sci1_rcv ipl)? bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.4 sci 1 receiver error interrupt priority level (sci1_rerr ipl)? bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.5 reserved?bits 7?6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.6.6 sci 1 transmitter idle interrupt priority level (sci1_tidl ipl)? bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 97 preliminary 5.6.6.7 sci 1 transmitter empty interrupt priority level (sci1_xmit ipl)? bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.8 spi 0 transmitter empty interrupt priority level (spi0_xmit ipl)? bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7 interrupt priority register 6 (ipr6) figure 5-9 interrupt priority register 6 (ipr6) 5.6.7.1 timer c, channel 0 interrupt priority level (tmrc0 ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmrc0 ipl tmrd3 ipl tmrd2 ipl tmrd1 ipl tmrd0 ipl 0 0 dec0_xirq ipl dec0_hirq ipl write reset 0000000000000000
56f8366 technical data, rev. 2.0 98 freescale semiconductor preliminary 5.6.7.2 timer d, channel 3 interrupt priority level (tmrd3 ipl)?bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.3 timer d, channel 2 interrupt priority level (tmrd2 ipl)?bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.4 timer d, channel 1 interrupt priority level (tmrd1 ipl)?bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.5 timer d, channel 0 interrupt priority level (tmrd0 ipl)?bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.6 reserved?bits 5?4 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing.
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 99 preliminary 5.6.7.7 quadrature decoder 0, index pulse interrupt priority level (dec0_xirq ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.8 quadrature decoder 0, home signal transition or watchdog timer interrupt priority level (dec0_hirq ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8 interrupt priority register 7 (ipr7) figure 5-10 interrupt priority register (ipr7) 5.6.8.1 timer a, channel 0 interrupt priority level (tmra0 ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmra0 ipl tmrb3 ipl tmrb2 ipl tmrb1 ipl tmrb0 ipl tmrc3 ipl tmrc2 ipl tmrc1 ipl write reset 0000000000000000
56f8366 technical data, rev. 2.0 100 freescale semiconductor preliminary 5.6.8.2 timer b, channel 3 interrupt priority level (tmrb3 ipl)?bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.3 timer b, channel 2 interrupt priority level (tmrb2 ipl)?bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.4 timer b, channel 1 interrupt priority level (tmrb1 ipl)?bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.5 timer b, channel 0 interrupt priority level (tmrb0 ipl)?bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 101 preliminary 5.6.8.6 timer c, channel 3 interrupt priority level (tmrc3 ipl)?bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.7 timer c, channel 2 interrupt priority level (tmrc2 ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.8 timer c, channel 1 interrupt priority level (tmrc1 ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9 interrupt priority register 8 (ipr8) figure 5-11 interrupt priority register 8 (ipr8) 5.6.9.1 sci0 receiver full interrupt priority level (sci0_rcv ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read sci0_rcv ipl sci0_rerr ipl 0 0 sci0_tidl ipl sci0_xmit ipl tmra3 ipl tmra2 ipl tmra1 ipl write reset 0000000000000000
56f8366 technical data, rev. 2.0 102 freescale semiconductor preliminary 5.6.9.2 sci0 receiver error interrupt priority level (sci0_rerr ipl)? bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.3 reserved?bits 11?10 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.9.4 sci0 transmitter idle interrupt priority level (sci0_tidl ipl)? bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.5 sci0 transmitter empty interrupt priority level (sci0_xmit ipl)? bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.6 timer a, channel 3 interrupt priority level (tmra3 ipl)?bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 103 preliminary 5.6.9.7 timer a, channel 2 interrupt priority level (tmra2 ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.8 timer a, channel 1 interrupt priority level (tmra1 ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10 interrupt priority register 9 (ipr9) figure 5-12 interrupt priority register 9 (ipr9) 5.6.10.1 pwm a fault interrupt priority level (pwma_f ipl)?bits 15?14 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.2 pwm b fault interrupt priority level (pwmb_f ipl)?bits 13?12 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pwma_f ipl pwmb_f ipl pwma_rl ipl pwm_rl ipl adca_zc ipl abcb_zc ipl adca_cc ipl adcb_cc ipl write reset 0000000000000000
56f8366 technical data, rev. 2.0 104 freescale semiconductor preliminary 5.6.10.3 reload pwm a interrupt priority level (pwma_rl ipl)?bits 11?10 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.4 reload pwm b interrupt priority level (pwmb_rl ipl)?bits 9?8 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.5 adc a zero crossing or limit error interrupt priority level (adca_zc ipl)?bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.6 adc b zero crossing or limit error interrupt priority level (adcb_zc ipl)?bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 105 preliminary 5.6.10.7 adc a conversion complete interrupt priority level (adca_cc ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.8 adc b conversion complete interrupt priority level (adcb_cc ipl)?bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.11 vector base address register (vba) figure 5-13 vector base address register (vba) 5.6.11.1 reserved?bits 15?13 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.11.2 interrupt vector base address (vector base address)?bits 12?0 the contents of this register determine the location of the vector address table. the value in this register is used as the upper 13 bits of the interrupt vector address bus (vab[20:0]). the lower eight bits are determined based upon the highest-priority interrupt. they are then appended onto vba before presenting the full vab to the 56800e core; see part 5.3.1 for details. base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 vector base address write reset 0000000000000000
56f8366 technical data, rev. 2.0 106 freescale semiconductor preliminary 5.6.12 fast interrupt 0 match register (fim0) figure 5-14 fast interrupt 0 match register (fim0) 5.6.12.1 reserved?bits 15?7 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.12.2 fast interrupt 0 vector number (fast interrupt 0)?bits 6?0 this value determines which irq will be a fast interr upt 0. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first; see part 5.3.3 . irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any othe r priority. fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq, refer to table 4-5 . 5.6.13 fast interrupt 0 vector address low register (fival0) figure 5-15 fast interrupt 0 vector address low register (fival0) 5.6.13.1 fast interrupt 0 vector address low (fival0)?bits 15?0 the lower 16 bits of the vector address used for fast interrupt 0. this register is combined with fivah0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.6.14 fast interrupt 0 vector address high register (fivah0) figure 5-16 fast interrupt 0 vector address high register (fivah0) base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000 base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 107 preliminary 5.6.14.1 reserved?bits 15?5 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.14.2 fast interrupt 0 vector address high (fivah0)?bits 4?0 the upper five bits of the vector address used for fast interrupt 0. this register is combined with fival0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.6.15 fast interrupt 1 match register (fim1) figure 5-17 fast interrupt 1 match register (fim1) 5.6.15.1 reserved?bits 15?7 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. 5.6.15.2 fast interrupt 1 vector number (fast interrupt 1)?bits 6?0 this value determines which irq will be a fast interr upt 1. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first; see part 5.3.3 . irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any othe r priority. fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq, refer to table 4-5 . 5.6.16 fast interrupt 1 vector address low register (fival1) figure 5-18 fast interrupt 1 vector address low register (fival1) 5.6.16.1 fast interrupt 1 vector address low (fival1)?bits 15?0 the lower 16 bits of vector address are used for fast interrupt 1. this register is combined with fivah1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000 base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000
56f8366 technical data, rev. 2.0 108 freescale semiconductor preliminary 5.6.17 fast interrupt 1 vector address high register (fivah1) figure 5-19 fast interrupt 1 vector address high register (fivah1) 5.6.17.1 reserved?bits 15?5 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.17.2 fast interrupt 1 vector address high (fivah1)?bits 4?0 the upper five bits of the vector address are used fo r fast interrupt 1. this register is combined with fival1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.6.18 irq pending 0 register (irqp0) figure 5-20 irq pending 0 register (irqp0) 5.6.18.1 irq pending (pending)?bits 16?2 this register combines with the other five to repr esent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.18.2 reserved?bit 0 this bit is reserved or not implemented. it is read as 1 and cannot be modified by writing. 5.6.19 irq pending 1 register (irqp1) figure 5-21 irq pending 1 register (irqp1) base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [16:2] 1 write reset 1111111111111111 $base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [32:17] write reset 1111111111111111
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 109 preliminary 5.6.19.1 irq pending (pending)?bits 32?17 this register combines with the other five to repr esent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.20 irq pending 2 register (irqp2) figure 5-22 irq pending 2 register (irqp2) 5.6.20.1 irq pending (pending)?bits 48?33 this register combines with the other five to repr esent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.21 irq pending 3 register (irqp3) figure 5-23 irq pending 3 register (irqp3) 5.6.21.1 irq pending (pending)?bits 64?49 this register combines with the other five to repr esent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [48:33] write reset 1111111111111111 base + $14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [64:49] write reset 1111111111111111
56f8366 technical data, rev. 2.0 110 freescale semiconductor preliminary 5.6.22 irq pending 4 register (irqp4) figure 5-24 irq pending 4 register (irqp4) 5.6.22.1 irq pending (pending)?bits 80?65 this register combines with the other five to repr esent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.23 irq pending 5 register (irqp5) figure 5-25 irq pending register 5 (irqp5) 5.6.23.1 reserved?bits 96?86 this bit field is reserved or not implemented. the bi ts are read as 1 and cannot be modified by writing. 5.6.23.2 irq pending (pending)?bits 81?85 this register combines with the other five to repr esent the pending irqs for interrupt vector numbers 2 through 85. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.24 reserved ?base + 17 5.6.25 reserved ?base + 18 5.6.26 reserved ?base + 19 5.6.27 reserved ?base + 1a base + $15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [80:65] write reset 1111111111111111 base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 pending[81:85] write reset 111111111111111 1
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 111 preliminary 5.6.28 reserved ?base + 1b 5.6.29 reserved ?base + 1c 5.6.30 itcn control register (ictl) figure 5-26 itcn control register (ictl) 5.6.30.1 interrupt (int)?bit 15 this read-only bit reflects the state of the interrupt to the 56800e core. ? 0 = no interrupt is being sent to the 56800e core ? 1 = an interrupt is being sent to the 56800e core 5.6.30.2 interrupt priority level (ipic)?bits 14?13 these read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800e core at the time the last irq was taken. this fiel d is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be updated before the original interrupt service routine can read it. ? 00 = required nested exception priority levels are 0, 1, 2, or 3 ? 01 = required nested exception priority levels are 1, 2, or 3 ? 10 = required nested exception priority levels are 2 or 3 ? 11 = required nested exception priority level is 3 5.6.30.3 vector number - vector address bus (vab)?bits 12?6 this read-only field shows the vector number (vab[7:1]) used at the time the last irq was taken. this field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.4 interrupt disable (int_dis)?bit 5 this bit allows all interrupts to be disabled. ? 0 = normal operation (default) ? 1 = all interrupts disabled base + $1d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int ipic vab int_dis 1 irqb state irqa state irqb edg irqa edg write reset 0 0 0 1000000 0 1 1 1 0 0
56f8366 technical data, rev. 2.0 112 freescale semiconductor preliminary 5.6.30.5 reserved?bit 4 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 5.6.30.6 irqb state pin (irqb state)?bit 3 this read-only bit reflects the state of the external irqb pin. 5.6.30.7 irqa state pin (irqa state)?bit 2 this read-only bit reflects the state of the external irqa pin. 5.6.30.8 irqb edge pin (irqb edg)?bit 1 this bit controls whether the external irqb interrupt is edge- or level-sensitive. during stop and wait modes, it is automatically level-sensitive. ?0 = irqb interrupt is a low-level sensitive (default) ?1 = irqb interrupt is falling-edge sensitive 5.6.30.9 irqa edge pin (irqa edg)?bit 0 this bit controls whether the external irqa interrupt is edge- or level-sensitive. during stop and wait modes, it is automatically level -ensitive. ?0 = irqa interrupt is a low-level sensitive (default) ?1 = irqa interrupt is falling-edge sensitive 5.6.31 reserved ?base + $1e 5.6.32 interrupt priority register 10 (ipr10) note : this register is not available in the 56f8166 device. 5.6.32.1 reserved?bits 15?8 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. base + $1f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 flecan2_ msgbuf ipl flecan2_ wkup ipl flecan2_ err ipl flecan2_ boff ipl write reset 0001000000000000
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 113 preliminary 5.6.32.2 flexcan2 message buffer interrupt priority level (flexcan2_msgbuf ipl)?bits 7?6 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.32.3 flexcan2 wake up interrupt priority level (flexcan2_wkup ipl)? bits 5?4 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.32.4 flexcan2 error interrupt priority level (flexcan2_err ipl)?bits 3?2 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.32.5 flexcan2 bus-off interrupt priority level (flexcan2_boff ipl)? bits 1?0 this field is used to set the interrupt priority leve l for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8366 technical data, rev. 2.0 114 freescale semiconductor preliminary 5.7 resets 5.7.1 reset handshake timing the itcn provides the 56800e core with a reset vector address whenever reset is asserted. the reset vector will be presented until the second rising clock edge after reset is released. 5.7.2 itcn after reset after reset, all of the itcn registers are in their default states. this means all interrupts are disabled, except the core irqs with fixed priorities: ? illegal instruction ? sw interrupt 3 ? hw stack overflow ? misaligned long word access ? sw interrupt 2 ? sw interrupt 1 ? sw interrupt 0 ? sw interrupt lp these interrupts are enabled at their fixed priority levels. part 6 system integration module (sim) 6.1 overview the sim module is a system catchall for the glue logic that ties together the system-on-chip. it controls distribution of resets and clocks and provides a numbe r of control features. the system integration module is responsible for the following functions: ? reset sequencing ? clock generation & distribution ? stop/wait control ? pull-up enables for selected peripherals ? system status registers ? registers for software access to the jtag id of the chip ? enforcing flash security there are discussed in more detail in the sections that follow.
features 56f8366 technical data, rev. 2.0 freescale semiconductor 115 preliminary 6.2 features the sim has the following features: ? flash security feature prevents unauthorized access to code/data contained in on-chip flash memory ? power-saving clock gating for peripheral ? three power modes (run, wait, stop) to control power utilization ? stop mode shuts down the 56800e core, system clock, peripheral clock, and pll operation ? stop mode entry can optionally disable pll and oscillator (low power vs. fast restart); must be explicitly done ? wait mode shuts down the 56800e core and unnecessary system clock operation ? run mode supports full part operation ? controls to enable/disable the 56800e core wait and stop instructions ? calculates base delay for reset extension based upon por or reset operations. reset delay will be either 3 x 32 clocks (phased release of reset) for reset, except for por, which is 2 21 clock cycles. ? controls reset sequencing after reset ? software-initiated reset ? four 16-bit registers reset only by a power-on reset usable for general purpose software control ? system control register ? registers for software access to the jtag id of the chip 6.3 operating modes since the sim is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and ta ke appropriate action. these are: ? reset mode, which has two submodes: ? por and reset operation the 56800e core and all peripherals are reset. this occurs when the internal por is asserted or the reset pin is asserted. ? cop reset and software reset operation the 56800e core and all peripherals are reset. the ma bit within the omr is not changed. this allows the software to determine the boot mode (internal or external boot) to be used on the next reset. ? run mode this is the primary mode of operation for this device. in this mode, the 56800e controls chip operation. ? debug mode the 56800e is controlled via jtag/eonce when in debug mode. all peripherals, except the cop and pwms, continue to run. cop is disabled and pwm outputs are optionally switched off to disable any motor from being driven; see the pwm chapter in the 56f8300 peripheral user manual for details. ? wait mode in wait mode, the core clock and memory clocks are disabled. optionally, the cop can be stopped. similarly, it is an option to switch off pwm outputs to disable any motor from being driven. all other peripherals continue to run.
56f8366 technical data, rev. 2.0 116 freescale semiconductor preliminary ? stop mode when in stop mode, the 56800e core, memory, and most peripheral clocks are shut down. optionally, the cop and can can be stopped. for lowest power consumption in stop mode, the pll can be shut down. this must be done explicitly before entering stop mode, since there is no automatic mechanism for this. the can (along with any non-gated interrupt) is capable of waking the chip up from stop mode, but is not fully functional in stop mode. 6.4 operating mode register figure 6-1 omr the reset state for mb and ma will depend on the flash secured state. see part 4.2 and part 7 for detailed information on how the operating mode register (omr ) ma and mb bits operate in this device. for additional information, see the dsp56800e reference manual . note: the omr is not a memory map register; it is directly accessible in code through the acronym omr. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nl cm xp sd r sa ex 0 mb ma type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 000 0 0 00000000 0xx
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 117 preliminary 6.5 register descriptions table 6-1 sim registers (sim_base = $00 f350) address offset address acronym register name section location base + $0 sim_control control register 6.5.1 base + $1 sim_rststs reset status register 6.5.2 base + $2 sim_scr0 software control register 0 6.5.3 base + $3 sim_scr1 software control register 1 6.5.3 base + $4 sim_scr2 software control register 2 6.5.3 base + $5 sim_scr3 software control register 3 6.5.3 base + $6 sim_msh_id most significant half of jtag id 6.5.4 base + $7 sim_lsh_id least significant half of jtag id 6.5.5 base + $8 sim_pudr pull-up disable register 6.5.6 reserved base + $a sim_clkosr clko select register 6.5.7 base + $b sim_gps gpio peripheral select register 6.5.7 base + $c sim_pce peripheral clock enable register 6.5.8 base + $d sim_isalh i/o short address location high register 6.5.9 base + $e sim_isall i/o short address location low register 6.5.10 base + $f sim_pce2 peripheral clock enable register 2 6.5.11
56f8366 technical data, rev. 2.0 118 freescale semiconductor preliminary 6.5.1 sim control register (sim_control) figure 6-3 sim control register (sim_control) 6.5.1.1 reserved?bits 15?7 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 sim_ control r 0 0 0 0 0 0 0 0 0 emi_ mode once ebl 0 sw rst stop_ disable wait_ disable w $1 sim_ rststs r 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 w $2 sim_scr0 r field w $3 sim_scr1 r field w $4 sim_scr2 r field w $5 sim_scr3 r field w $6 sim_msh_ id r 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 w $7 sim_lsh_id r 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 w $8 sim_pudr r 0 pwma 1 can emi_ mode reset irq xboot pwmb pwma 0 0 ctrl 0 jtag 0 0 0 w reserved $a sim_ clkosr r 0 0 0 0 0 0 a23 a22 a21 a20 clkdis clkosel w $b sim_gps r 0 0 0 0 0 0 0 0 0 0 d1 d0 c3 c2 c1 c0 w $c sim_pce r emi adcb adca can dec1 dec0 tmrd tmrc tmrb tmra sci1 sci0 spi1 spi0 pwm b pwm a w $d sim_isalh r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 isal[23:22] w $e sim_isall r isal[21:6] w $f sim_pce2 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can2 w = reserved figure 6-2 sim register map summary base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 emi_ mode once ebl sw rst stop_ disable wait_ disable write reset 000000000 0 000000
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 119 preliminary 6.5.1.2 emi_mode (emi_mode)?bit 6 this bit reflects the current (non-clocked) state of the emi_mode pin. during reset, this bit, coupled with the extboot signal, is used to initialize address bits [19:16] either as gpio or as address. these settings can be explicitly overwritten using the appropriate gpio peripheral enable register at any time after reset. in addition, this pin can be used as a general purpose input pin after reset. ? 0 = external address bits [19:16] are initially programmed as gpio ? 1 = when booted with extboot = 1, a[19:16] are initially programmed as address. if extboot is 0, they are initialized as gpio. 6.5.1.3 once enable (once ebl)?bit 5 ? 0 = once clock to 56800e core enabled when core tap is enabled ? 1 = once clock to 56800e core is always enabled 6.5.1.4 software reset (sw rst)?bit 4 this bit is always read as 0. writing a 1 to this bit will cause the part to reset. 6.5.1.5 stop disable (stop_disable)?bits 3?2 ? 00 - stop mode will be entered when the 56800e core executes a stop instruction ? 01 - the 56800e stop instruction will not cause entry into stop mode; stop_disable can be reprogrammed in the future ? 10 - the 56800e stop instruction will not cause entry into stop mode; stop_disable can then only be changed by resetting the device ? 11 - same operation as 10 6.5.1.6 wait disable (wait_disable)?bits 1?0 ? 00 - wait mode will be entered when the 56800e core executes a wait instruction ? 01 - the 56800e wait instruction will not cause entry into wait mode; wait_disable can be reprogrammed in the future ? 10 - the 56800e wait instruction will not cause entry into wait mode; wait_disable can then only be changed by resetting the device ? 11 - same operation as 10 6.5.2 sim reset status register (sim_rststs) bits in this register are set upon any system reset and are initialized only by a power-on reset (por). a reset (other than por) will only set bits in the register ; bits are not cleared. only software should clear this register. figure 6-4 sim reset status register (sim_rststs) base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 write reset 0000000000 00
56f8366 technical data, rev. 2.0 120 freescale semiconductor preliminary 6.5.2.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.2.2 software reset (swr)?bit 5 when 1, this bit indicates that the previous reset occurr ed as a result of a software reset (write to sw rst bit in the sim_control register). this bit will be cleared by any hardware reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.3 cop reset (copr)?bit 4 when 1, the copr bit indicates the computer operating properly (cop) timer-generated reset has occurred. this bit will be cleared by a power-on reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 external reset (extr)?bit 3 if 1, the extr bit indicates an external system rese t has occurred. this bit will be cleared by a power-on reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit position will clear it. basically, when the extr bit is 1, the previous system reset was caused by the external reset pin being asserted low. 6.5.2.5 power-on reset (por)?bit 2 when 1, the por bit indicates a power-on reset occurre d some time in the past. this bit can be cleared only by software or by another type of reset. writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. in summary, if the bit is 1, the previous system reset was due to a power-on reset. 6.5.2.6 reserved?bits 1?0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.3 sim software control registers (sim_scr0, sim_scr1, sim_scr2, and sim_scr3) only sim_scr0 is shown below. sim_scr1, sim_scr2, and sim_scr3 are identical in functionality. figure 6-5 sim software control register 0 (sim_scr0) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read field write por 0000000000000000
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 121 preliminary 6.5.3.1 software control data 1 (field)?bits 15?0 this register is reset only by the power-on reset (por). it has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (reset pin, software reset, and cop reset). 6.5.4 most significant half of jtag id (sim_msh_id) this read-only register displays the most significant ha lf of the jtag id for the chip. this register reads $01d6. figure 6-6 most significant half of jtag id (sim_msh_id) 6.5.5 least significant half of jtag id (sim_lsh_id) this read-only register displays the least significant ha lf of the jtag id for the chip. this register reads $d01d. figure 6-7 least significant half of jtag id (sim_lsh_id) 6.5.6 sim pull-up disable register (sim_pudr) most of the pins on the chip have on-chip pull-up resi stors. pins which can operate as gpio can have these resistors disabled via the gpio function. non-gpio pins can have their pull-ups disabled by setting the appropriate bit in this register. disabling pull-ups is done on a peripheral-by-peri pheral basis (for pins not muxed with gpio). each bit in the register (see figure 6-8 ) corresponds to a functional group of pins. see table 2-2 to identify which pins can deactivate the internal pull-up resistor. figure 6-8 sim pull-up disable register (sim_pudr) base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0000000111010110 write reset 0000000111010110 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1101000000011101 write reset 1101000000011101 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 pwma1 can emi_ mode reset irq xboot pwmb pwma0 0 ctrl 0 jtag 000 write reset 0000 000 0 0 0000000
56f8366 technical data, rev. 2.0 122 freescale semiconductor preliminary 6.5.6.1 reserved ?bit 15 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.6.2 pwma1?bit 14 this bit controls the pull-up resistors on the faulta3 pin. 6.5.6.3 can?bit 13 this bit controls the pull-up resistors on the can_rx pin. 6.5.6.4 emi_mode?bit 12 this bit controls the pull-up resistors on the emi_mode pin. 6.5.6.5 reset ?bit 11 this bit controls the pull-up resistors on the reset pin. 6.5.6.6 irq?bit 10 this bit controls the pull-up resistors on the irqa and irqb pins. 6.5.6.7 xboot?bit 9 this bit controls the pull-up resistors on the extboot pin. note: in this package, this input pin is double-bonded with the adjacent v ss pin and this bit should be changed to a 1 in order to reduce power consumption. 6.5.6.8 pwmb?bit 8 this bit controls the pull-up resistors on th e faultb0, faultb1, fau ltb2, and faultb3 pins. 6.5.6.9 pwma0?bit 7 this bit controls the pull-up resistors on the faulta0, faulta1, and faulta2 pins. 6.5.6.10 reserved?bit 6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.6.11 ctrl?bit 5 this bit controls the pull-up resistors on the wr and rd pins. 6.5.6.12 reserved?bit 4 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.6.13 jtag?bit 3 this bit controls the pull-up resistors on the trst , tms and tdi pins.
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 123 preliminary 6.5.6.14 reserved?bit 2?0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.7 clko select register (sim_clkosr) the clko select register can be used to multiplex out any one of the clocks generated inside the clock generation and sim modules. the defa ult value is sys_clk. all other clocks primarily muxed out are for test purposes only, and are subject to signifi cant unspecified latenc ies at high frequencies. the upper four bits of the gpiob register can func tion as gpio, a[23:20], or as additional clock output signals. gpio has priority and is enabled/disabled via the gpiob_per. if gpio b[7:4] are programmed to operate as peripheral outputs, then the choice between a[23:20] and additional clock outputs is done here in the clkosr. the default state is for the pe ripheral function of gpio b[ 7:4] to be programmed as a[23:20]. this can be changed by altering a[23:20] as shown in figure 6-9 . figure 6-9 clko select register (sim_clkosr) 6.5.7.1 reserved?bits 15?10 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.7.2 alternate gpiob peripheral function for a23 (a23)?bit 9 ? 0 = peripheral output function of gpio b7 is defined to be a23 ? 1 = peripheral output function of gpio b7 is defined to be the oscillator clock (mstr_osc; see figure 3-4 ) 6.5.7.3 alternate gpiob peripheral function for a22 (a22)?bit 8 ? 0 = peripheral output function of gpiob6 is defined to be a22 ? 1 = peripheral output function of gpiob6 is defined to be sys_clk2 6.5.7.4 alternate gpiob peripheral function for a21 (a21)?bit 7 ? 0 = peripheral output function of gpiob5 is defined to be a21 ? 1 = peripheral output function of gpiob5 is defined to be sys_clk 6.5.7.5 alternate gpiob peripheral function for a20 (a20)?bit 6 ? 0 = peripheral output function of gpiob4 is defined to be a20 ? 1 = peripheral output function of gpiob4 is defined to be the prescaler clock (fref; see figure 3-4 ) base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 a23 a22 a21 a20 clk dis clkosel write reset 0000000000100000
56f8366 technical data, rev. 2.0 124 freescale semiconductor preliminary 6.5.7.6 clockout disable (clkdis)?bit 5 ? 0 = clkout output is enabled and will output the signal indicated by clkosel ? 1 = clkout is tri-stated 6.5.7.7 clockout select (clkosel)?bits 4?0 selects clock to be muxed out on the clko pin. ? 00000 = sys_clk (from occs - default) ? 00001 = reserved for factory test?56800e clock ? 00010 = reserved for factory test?xram clock ? 00011 = reserved for factory test?pflash odd clock ? 00100 = reserved for factory test?pflash even clock ? 00101 = reserved for factory test?bflash clock ? 00110 = reserved for factory test?dflash clock ? 00111 = oscillator output ? 01000 = f out (from occs) ? 01001 = reserved for factory test?ipb clock ? 01010 = reserved for factory test?feedback (from occs, this is path to pll) ? 01011 = reserved for factory test?prescaler clock (from occs) ? 01100 = reserved for factory test?postscaler clock (from occs) ? 01101 = reserved for factory test?sys_clk2 (from occs) ? 01110 = reserved for factory test?sys_clk_div2 ? 01111 = reserved for factory test?sys_clk_d ? 10000 = adca clock ? 10001 = adcb clock 6.5.8 gpio peripheral select register (sim_gps) some gpio pads can have more th an one peripheral selected as the alternate function instead of gpio. for these pads, this register selects which of the al ternate peripherals are actually selected for the gpio peripheral function. this applies to gpioc, pins 0-3, and to gpiod, pins 0 and 1. the gpioc peripheral select register can be used to multiplex out any one of the three alternate peripherals for gpioc. the default peripheral is quad decoder 1 and quad timer b ( not available in the 56f8166 device ); these peripherals work together. the four i/o pins associated with gpioc can function as gpio, quad decoder 1/quad timer b , or as spi 1 signals. gpio is not the default and is enabled/disabled via the gpioc_per, as shown in figure 6-10 and table 6-2 . when gpioc[3:0] are programmed to operate as peripheral i/o, then the choice between decoder/timer and spi inputs/outputs is made in the sim_gps register and in conjunction with the quad timer status and control registers (s cr). the default state is for the peripheral function of gpioc[3:0] to be programmed as decoder functions. this can be changed by altering the appropriate controls in the indicated registers.
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 125 preliminary figure 6-10 overall control of gpioc pads using sim_gps control table 6-2 control of gpioc pads using sim_gps control 1 1. this applies to the four pins that serve as quad decoder / quad timer / spi / gpioc functions. a separate set of control bits is used for each pin. pin function control registers comments gpioc_per gpioc_dtr sim_gps quad timer scr register oen bits gpio input 0 0 ? ? gpio output 0 1 ? ? quad timer input / quad decoder input 2 2. reset configuration 1 ? 0 0 see the ?switch matrix for inputs to the timer? table in the 56f8300 peripheral user manual for the definition of timer inputs based on the quad decoder mode configuration. quad timer output / quad decoder input 3 3. quad decoder pins are always inputs and function in conjunction with the quad timer pins. 1? 0 1 spi input 1 ? 1 ? see spi controls for determining the direction of each of the spi pins. spi output 1 ? 1 ? gpioc_per register gpio controlled i/o pad control sim_ gps register quad timer controlled spi controlled 0 1 0 1
56f8366 technical data, rev. 2.0 126 freescale semiconductor preliminary two input/output pins associated with gpiod can f unction as gpio, emi (default peripheral) or can2 (not available in the 56f8166 device) signals. gpio is the default and is enabled/disabled via the gpiod_per, as shown in figure 6-11 and table 6-3 . when gpiod[1:0] are programmed to operate as peripheral input/output, then the choice between emi and can2 inputs/outputs is made here in the gps. figure 6-11 overall control of gpiod pads using sim_gps control note: can2 is not available in the 56f8166 device. table 6-3 control of gpiod pads using sim_gps control 1 1. this applies to the two pins that serve as emi csn / can2 / gpiod functions. a separate set of control bits is used for each pin. pin function control registers comments gpiod_per gpioc_ddr sim_gps gpio input 0 0 ? gpio output 0 1 ? emi i/o 1 ? 0 emi csn pins are always outputs can2 1 ? 1 can2_tx is always an output can2_rx is always an input gpiod_per register gpio controlled i/o pad control sim_ gps register emi controlled can2 controlled 0 1 0 1
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 127 preliminary figure 6-12 gpio peripheral select register (sim_gps) 6.5.8.1 reserved?bits 15?6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.8.2 gpiod1 (d1)?bit 5 this bit selects the alternate function for gpiod1. ?0 = cs3 ? 1 = can2_rx 6.5.8.3 gpiod0 (d0)?bit 4 ?0 = cs2 ? 1 = can2_tx 6.5.8.4 gpioc3 (c3)?bit 3 this bit selects the alternate function for gpioc3. ? 0 = home1/tb3 (default - see ?switch matrix mode? bits of the quad decoder deccr register in the 56f8300 peripheral user manual ) ? 1 = ss1 6.5.8.5 gpioc2 (c2)?bit 2 this bit selects the alternate function for gpioc2. ? 0 = index1/tb2 (default) ?1 = miso1 6.5.8.6 gpioc1 (c1)?bit 1 this bit selects the alternate function for gpioc1. ? 0 = phaseb1/tb1 (default) ?1 = mosi1 base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 d1 d0 c3 c2 c1 c0 write reset 000000000000 0 0 0 0
56f8366 technical data, rev. 2.0 128 freescale semiconductor preliminary 6.5.8.7 gpioc0 (c0)?bit 0 this bit selects the alternate function for gpioc0. ? 0 = phasea1/tb0 (default) ?1 = sclk1 6.5.9 peripheral clock enable register (sim_pce) the peripheral clock enable register is used to enable or disable clocks to the peripherals as a power savings feature. the clocks can be individua lly controlled for each peripheral on the chip. figure 6-13 peripheral clock enable register (sim_pce) 6.5.9.1 external memory interface enable (emi)?bit 15 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.2 analog-to-digital converter b enable (adcb)?bit 14 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 analog-to-digital converter a enable (adca)?bit 13 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 flexcan enable (can)?bit 12 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read emi adcb adca can dec1 dec0 tmrd tmrc tmrb tmra sci 1 sci 0 spi 1 spi 0 pwmb pwma write reset 111111 1 1 1 111 1 1 1 1
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 129 preliminary 6.5.9.5 decoder 1 enable (dec1)?bit 11 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 decoder 0 enable (dec0)?bit 10 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.7 quad timer d enable (tmrd)?bit 9 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 quad timer c enable (tmrc)?bit 8 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.9 quad timer b enable (tmrb)?bit 7 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.10 quad timer a enable (tmra)?bit 6 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.11 serial communications interface 1 enable (sci1)?bit 5 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 serial communications interface 0 enable (sci0)?bit 4 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled)
56f8366 technical data, rev. 2.0 130 freescale semiconductor preliminary 6.5.9.13 serial peripheral interface 1 enable (spi1)?bit 3 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 serial peripheral interface 0 enable (spi0)?bit 2 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 pulse width modulator b enable (pwmb)?1 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 pulse width modulator a enable (pwma)?0 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.10 i/o short address location register (sim_isalh and sim_isall) the i/o short address location registers are used to specify the memory referenced via the i/o short address mode. the i/o short address mode allows the in struction to specify the lower six bits of address; the upper address bits are not directly controllable. this register set allows limited control of the full address, as shown in figure 6-14 . note: if this register is set to something other than the top of memory (eonce register space) and the ex bit in the omr is set to 1, the jtag port cannot access the on-chip eonce registers, and debug functions will be affected.
register descriptions 56f8366 technical data, rev. 2.0 freescale semiconductor 131 preliminary figure 6-14 i/o short address determination with this register set, an interrupt driver can set the sim_isall register pair to point to its peripheral registers and then use the i/o short addressing mode to reference them. the isr should restore this register to its previous contents prior to returning from interrupt. note: the default value of this register set points to the eonce registers. note: the pipeline delay between setting this register set and using short i/o addressing with the new value is three cycles. figure 6-15 i/o short address location high register (sim_isalh) 6.5.10.1 input/output short address low (isal[23:22])?bit 1?0 this field represents the upper two address b its of the ?hard coded? i/o short address. figure 6-16 i/o short address location low register (sim_isal) base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 isal[23:22] write reset 111111 1 1 1111 1 1 11 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read isal[21:6] write reset 111111 1 1 1111 1 1 11 instruction portion ? hard coded? address portion 6 bits from i/o short address mode instruction 16 bits from sim_isall register 2 bits from sim_isalh register full 24-bit for short i/o address
56f8366 technical data, rev. 2.0 132 freescale semiconductor preliminary 6.5.10.2 input/output short address low (isal[21:6])?bit 15?0 this field represents the lower 16 address bits of the ?hard coded? i/o short address. 6.5.11 peripheral clock enable register 2 (sim_pce2) the peripheral clock enable register 2 is used to enable or disable clocks to the peripherals as a power-saving feaure. the clocks can be individu ally controller for each peripheral on the chip. 6.5.11.1 reserved?bits 15?1 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.11.2 can2 enable?bit 0 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.6 clock generation overview the sim uses an internal master clock from the occs (clkgen) module to produce the peripheral and system (core and memory) clocks. the maximum ma ster clock frequency is 120mhz. peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60mhz. the sim provides power modes (stop, wait) and clock enables (sim_pce register, clk_dis, once_ebl) to control which clocks are in operation. the occs, power modes, and clock enables provide a flexible means to manage power consumption. power utilization can be minimized in several ways. in the occs, crystal oscillator, and pll may be shut down when not in use. when the pll is in use, its prescaler and postscaler can be used to limit pll and master clock frequency. power modes permit system and/ or peripheral clocks to be disabled when unused. clock enables provide the means to disable individua l clocks. some peripherals provide further controls to disable unused subfunctions. refer to the part 3 on-chip clock synthesis (occs) , and the 56f8300 peripheral user manual for further details. 6.7 power-down modes overview the 56f8366/56f8166 devices operate in one of three power-down modes, as shown in table 6-4 . base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 can 2 write reset 000000 0 0 0000 0 0 01
stop and wait mode disable function 56f8366 technical data, rev. 2.0 freescale semiconductor 133 preliminary all peripherals, except the cop/watchdog timer, run of f the ipbus clock frequency, which is the same as the main processor frequency in this arch itecture. the maximum frequency of operation is sys_clk = 60mhz. 6.8 stop and wait mode disable function figure 6-17 internal stop disable circuit table 6-4 clock operation in power-down modes mode core clocks peripheral clocks description run active active device is fully functional wait core and memory clocks disabled active peripherals are active and can product interrupts if they have not been masked off. interrupts will cause the core to come out of its suspended state and resume normal operation. typically used for power-conscious applications. stop system clocks continue to be generated in the sim, but most are gated prior to reaching memory, core and peripherals. the only possible recoveries from stop mode are: 1. can traffic (1st message will be lost) 2. non-clocked interrupts 3. cop reset 4. external reset 5. power-on reset d-flop dq c d-flop d q c r 56800e stop_dis permanent disable reprogrammable disable clock select reset note: wait disable circuit is similar
56f8366 technical data, rev. 2.0 134 freescale semiconductor preliminary the 56800e core contains both stop and wait inst ructions. both put the cpu to sleep. for lowest power consumption in stop mode, the pll can be shut down. this must be done explicitly before entering stop mode, since there is no automatic mechanis m for this. when the pll is shut down, the 56800e system clock must be set equal to the prescaler output. some applications require the 56800e stop and wait instructions be disabled. to disable those instructions, write to the sim control register (sim_control) described in part 6.5.1 . this procedure can be on either a permanent or temporary basis. pe rmanently assigned applications last only until their next reset. 6.9 resets the sim supports four sources of reset. the two asynchronous sources are the external reset pin and the power-on reset (por). the two synchronous sources are the software reset, which is generated within the sim itself by writing to the sim_control register, and the cop reset. reset begins with the assertion of a ny of the reset sources. release of reset to various blocks is sequenced to permit proper operation of the device. a por reset is first extended for 2 21 clock cycles to permit stabilization of the clock source, followed by a 32 cl ock window in which sim cl ocking is initiated. it is then followed by a 32 clock window in which periphera ls are released to implement flash security, and, finally, followed by a 32 clock window in which the core is initialized. after completion of the described reset sequence, application code will begin execution. resets may be asserted asynchronously, but they are always released internally on a rising edge of the system clock. part 7 security features the 56f8366/56f8166 offer security features intended to prevent unauthorized users from reading the contents of the flash memory (fm) array. the flash s ecurity consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the flash array. however, part of the security must lie with the user ?s code. an extreme example would be user?s code that dumps the contents of the internal program, as this code would defeat the purpose of security. at the same time, the user may also wish to put a ?backdoor? in his program. as an example, the user downloads a security key through the sci, allowing access to a programming routine that upda tes parameters stored in another section of the flash. 7.1 operation with security enabled once the user has programmed the flash with his application code, the device can be secured by programming the security bytes located in the fm c onfiguration field, which occupies a portion of the fm array. these non-volatile bytes will keep the part s ecured through reset and through power-down of the device. only two bytes within this field are used to enable or disable security. refer to the flash memory section in the 56f8300 peripheral user manual for the state of the security bytes and the resulting state of security. when flash security mode is enabled in accordance with the method described in the flash
flash access blocking mechanisms 56f8366 technical data, rev. 2.0 freescale semiconductor 135 preliminary memory module specification, the device will disable external p-space accesses restricting code execution to internal memory, disable extboot = 1 mode, a nd disable the core eonce debug capabilities. normal program execution is otherwise unaffected. 7.2 flash access blocking mechanisms the 56f8366/56f8166 have several operating functional a nd test modes. effective flash security must address operating mode selection a nd anticipate modes in which the on-chip flash can be compromised and read without explicit user permission. methods to block these are outlined in the next subsections. 7.2.1 forced operating mode selection at boot time, the sim determines in which functi onal modes the device will operate. these are: ? internal boot mode ? external boot mode ? secure mode when flash security is enabled as described in the flash memory module specification, the device will boot in internal boot mode, disable all access to external p-space, and start executing code from the boot flash at address 0x02_0000. this security affords protection only to applications in which the device operates in internal flash security mode. therefore, the security feature cannot be used unless all executing code resides on-chip. when security is enabled, any attempt to override the default internal opera ting mode by asserting the extboot pin in conjunction with reset will be ignored. 7.2.2 disabling eonce access on-chip flash can be read by issuing commands across the eonce port, which is the debug interface for the 56800e core. the trst , tclk, tms, tdo, and tdi pins comprise a jtag interface onto which the eonce port functionality is mapped. when the device boots, the chip-level jtag tap (test access port) is active and provides the chip?s boundary scan capability and access to the id register. proper implementation of flash security requires th at no access to the eonce port is provided when security is enabled. the 56800e core has an input which disables reading of internal memory via the jtag/eonce. the fm sets this input at reset to a va lue determined by the contents of the fm security bytes. 7.2.3 flash lockout recovery if a user inadvertently enables flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. this mechanis m completely reases all on-chip flash, thus disabling flash security. access to this recovery mechanism is built into codewarrior via an instruction in memory configuration (. cfg ) files. add, or uncomment the following configuration command: unlock_flash_on_connect 1 for more information, please see codewarrior mc56f83xx/dsp5685x family targeting manual .
56f8366 technical data, rev. 2.0 136 freescale semiconductor preliminary the lockout_recovery instruction has an associated 7-bit data register (dr) that is used to control the clock divider circuit within the fm module. this divider, fm_clkdiv[6:0], is used to control the period of the clock used for timed events in the fm erase algorithm. this register must be set with appropriate values before the lockout sequence can begin. refer to the jtag section of the 56f8300 peripheral user manual for more details on setting this register value. the value of the jtag fm_clkdiv[6:0] will replace th e value of the fm register fmclkd that divides down the system clock for timed events, as illustrated in figure 7-1 . fm_clkdiv[6] will map to the prdiv8 bit, and fm_clkdiv[5:0] will map to the div[5:0] bits. the combination of prdiv8 and div must divide the fm input clock down to a frequency of 150khz-200khz. the ?writing the fmclkd register ? section in the flash memory chapter of the 56f8300 peripheral user manual gives specific equations for calculating the correct values. figure 7-1 jtag to fm connection for lockout recovery two examples of fm_clkdiv calculations follow. example 1: if the system clock is the 8mhz crystal frequency because the pll has not been set up, the input clock will be below 12.8mhz, so prdiv8 = fm_clkdiv[6] = 0. using the following equation yields a div value of 19 for a clock of 200khz, and a div value of 20 for a clock of 190khz. this translates into an fm_clkdiv[6:0] value of $13 or $14, respectively. sys_clk jtag fmclkd divider 7 7 7 2 fm_clkdiv fm_erase flash memory clock input sys_clk (2) ) ( < < (div + 1) 150[khz] 200[khz]
introduction 56f8366 technical data, rev. 2.0 freescale semiconductor 137 preliminary example 2: in this example, the system clock has been set up with a value of 32mhz, making the fm input clock 16mhz. because that is greater th an 12.8mhz, prdiv8 = fm_clkdiv[6] = 1. using the following equation yields a div value of 9 for a cl ock of 200khz, and a div value of 10 for a clock of 181khz. this translates to an fm_clkdiv[6:0] value of $49 or $4a, respectively. once the lockout_recovery instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7- bit data register. after the data register has been updated, the user must transition the tap controller into the run-test/idle state for the lockout sequence to commence. the controller must remain in this state until the erase sequence has completed. for details, see the jtag section in the 56f8300 peripheral user manual . note: once the lockout recovery sequence has completed, the user must reset both the jtag tap controller (by asserting trst ) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 product analysis the recommended method of unsecuring a programmed device for product anal ysis of field failures is via the backdoor key access. the customer would need to supply technical support with the backdoor key and the protocol to access the backdoor routine in the flash. additionally, the keyen bit that allows backdoor key access must be set. an alternative method for performing analysis on a se cured hybrid controller would be to mass-erase and reprogram the flash with the original code, but modify the security bytes. to insure that a customer does not inadvertently lock himself out of the device during programming, it is recommended that he program the ba ckdoor access key first, his applic ation code second, and the security bytes within the fm configuration field last. part 8 general purpose input/output (gpio) 8.1 introduction this section is intended to supplement the gpio information found in the 56f8300 peripheral user manual and contains only chip-specific information. this information supercedes the generic information in the 56f8300 peripheral user manual . ) ( < < (div + 1) 150[khz] 200[khz] sys_clk (2)(8)
56f8366 technical data, rev. 2.0 138 freescale semiconductor preliminary 8.2 memory maps the width of the gpio port defines how many bits are implemented in each of the gpio registers. based on this and the default function of each of the gp io pins, the reset values of the gpiox_pur and gpiox_per registers change from port to port. tables 4-29 through 4-34 define the actual reset values of these registers. 8.3 configuration there are six gpio ports defined on the 56f8366/ 56f8166. the width of each port and the associated peripheral function is shown in table 8-1 and table 8-2 . the specific mapping of gpio port pins is shown in table 8-3 . table 8-1 56f8366 gpio ports configuration gpio port port width available pins in 56f8366 peripheral function reset function a14 14 14 pins - emi address pins emi address b8 1 1 pin - emi address pin 7 pins - emi address pins - not available in this package emi address n/a c11 11 4 pins -dec1 / tmrb / spi1 4 pins -dec0 / tmra 3 pins -pwma current sense dec1 / tmrb dec0 / tmra pwma current sense d13 9 2 pins - emi csn 4 pins - emi csn - not available in this package 2 pins - sci1 2 pins - emi csn 3 pins -pwmb current sense emi chip selects n/a sci1 emi chip selects pwmb current sense e 14 11 2 pins - sci0 2 pins - emi address pins 4 pins - spi0 1 pin - tmrc 1 pin - tmrc - not available in this package 2 pins - tmrd 2 pins - tmrd - not available in this package sci0 emi address spi0 tmrc n/a tmrd n/a f16 16 16 pins - emi data emi data
configuration 56f8366 technical data, rev. 2.0 freescale semiconductor 139 preliminary table 8-2 56f8166 gpio ports configuration gpio port port width available pins in 56f8166 peripheral function reset function a14 14 14 pins - emi address pins emi address b8 1 1 pin - emi address pin 7 pins - emi address pins - not available in this package emi address n/a c11 11 4 pins - spi1 4 pins - dec0 / tmra 3 pins - dedicated gpio spi1 dec0 / tmra gpio d13 9 2 pins - emi csn 4 pins - emi csn - not available in this package 2 pins - sci1 2 pins - emi csn 3 pins - pwmb current sense emi chip selects n/a sci1 emi chip selects pwmb current sense e 14 11 2 pins - sci0 2 pins - emi address pins 4 pins - spi0 1 pin - tmrc 1 pin - tmrc - not available in this package 2 pins - dedicated gpio 2 pins - tmrd - not available in this package sci0 emi address spi0 tmrc n/a gpio n/a f16 16 16 pins - emi data emi data
56f8366 technical data, rev. 2.0 140 freescale semiconductor preliminary table 8-3 gpio external signals map pins in shaded rows are not available in 56f8366/56f8166 pins in italics are not available in the 56f8166 device gpio port gpio bit reset function functional signal package pin gpioa 0 peripheral a8 19 1 peripheral a9 20 2 peripheral a10 21 3 peripheral a11 22 4 peripheral a12 23 5 peripheral a13 24 6 peripheral a14 25 7 peripheral a15 26 8 peripheral a0 138 9 peripheral a1 10 10 peripheral a2 11 11 peripheral a3 12 12 peripheral a4 13 13 peripheral a5 14 gpiob 0 gpio 1 a16 33 1 n/a 2 n/a 3 n/a 4 n/a 5 n/a 6 n/a 7 n/a 1 this is a function of the emi_mode, extboot, and flash security settings at reset.
configuration 56f8366 technical data, rev. 2.0 freescale semiconductor 141 preliminary gpioc 0 peripheral phasea1 / tb0 / sclk1 1 6 1 peripheral phaseb1 / tb1 / mosi1 1 7 2 peripheral index1 / tb2 / miso1 1 8 3 peripheral home1 / tb3 / ss1 1 9 4 peripheral phasea0 / ta0 139 5 peripheral phaseb0 / ta1 140 6 peripheral index0 / ta2 141 7 peripheral home0 / ta3 142 8 peripheral isa0 113 9 peripheral isa1 114 10 peripheral isa2 115 gpiod 0 gpio cs2 / can2_tx 48 1 gpio cs3 / can2_rx 49 2 n/a 3 n/a 4 n/a 5 n/a 6 peripheral txd1 42 7 peripheral rxd1 43 8 peripheral ps / cs0 46 9 peripheral ds / cs1 47 10 peripheral isb0 50 11 peripheral isb1 52 12 peripheral isb2 53 table 8-3 gpio external signals map (continued) pins in shaded rows are not available in 56f8366/56f8166 pins in italics are not available in the 56f8166 device gpio port gpio bit reset function functional signal package pin
56f8366 technical data, rev. 2.0 142 freescale semiconductor preliminary gpioe 0 peripheral txd0 4 1 peripheral rxd0 5 2 peripheral a6 17 3 peripheral a7 18 4 peripheral sclk0 130 5 peripheral mosi0 132 6 peripheral miso0 131 7 peripheral ss0 129 8 peripheral tc0 118 9 n/a 10 peripheral td0 116 11 peripheral td1 117 12 n/a 13 n/a table 8-3 gpio external signals map (continued) pins in shaded rows are not available in 56f8366/56f8166 pins in italics are not available in the 56f8166 device gpio port gpio bit reset function functional signal package pin
jtag information 56f8366 technical data, rev. 2.0 freescale semiconductor 143 preliminary part 9 joint test action group (jtag) 9.1 jtag information please contact your freescale marketing repr esentative or authorized distributor for device/package-specific bsdl information. gpiof 0 peripheral d7 28 1 peripheral d8 29 2 peripheral d9 30 3 peripheral d10 32 4 peripheral d11 133 5 peripheral d12 134 6 peripheral d13 135 7 peripheral d14 136 8 peripheral d15 137 9 peripheral d0 59 10 peripheral d1 60 11 peripheral d2 72 12 peripheral d3 75 13 peripheral d4 76 14 peripheral d5 77 15 peripheral d6 78 1. see part 6.5.8 to determine how to select peripherals from this set; dec1 is the selected peripheral at reset. table 8-3 gpio external signals map (continued) pins in shaded rows are not available in 56f8366/56f8166 pins in italics are not available in the 56f8166 device gpio port gpio bit reset function functional signal package pin
56f8366 technical data, rev. 2.0 144 freescale semiconductor preliminary part 10 specifications 10.1 general characteristics the 56f8366/56f8166 are fabricated in high-density cmos with 5v-tolerant ttl-compatible digital inputs. the term ?5v-tolerant? refers to the capab ility of an i/o pin, built on a 3.3v-compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v- and 5v-compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels combined with the ability to receive 5v levels without damage. absolute maximum ratings in table 10-1 are stress ratings only, and func tional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. note: all specifications meet both automotive and industrial requirements unless individual specifications are listed. note: the 56f8166 device is guaranteed to 40mhz and sp ecified to meet industrial requirements only. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
general characteristics 56f8366 technical data, rev. 2.0 freescale semiconductor 145 preliminary note: the 56f8166 device is guaranteed to 40mhz and sp ecified to meet industrial requirements only; can is not available on the 56f8166 device. note: pins in italics are not available in the 56f8166 device. pin group 1: txd0-1, rxd0-1, ss0 , miso0, mosi0 pin group 2: phasea0, phasea1 , phaseb0, phaseb1 , index0, index1 , home0, home1 , isb0-2, rsto , isa0-2, tc0, sclk0 pin group 3: rsto , tdo pin group 4: can_tx pin group 5: a0-5, d0-15, gpiod0-1, ps , ds pin group 6: a6-15, gpiob0, td0-1 pin group 7: clko, wr , rd pin group 8: pwma0-5 , pwmb0-5 pin group 9: irqa , irqb , reset , extboot, trst , tms, tdi, can_rx , emi_mode, faulta0-3 , faultb0-3 pin group 10: tck pin group 11: xtal, extal pin group 12: ana0-7, anb0-7 pin group 13: ocr_dis, clkmode table 10-1 absolute maximum ratings (v ss = v ssa_adc = 0) characteristic symbol notes min max unit supply voltage v dd_io - 0.3 4.0 v adc supply voltage v dda_adc, v refh v refh must be less than or equal to v dda_adc - 0.3 4.0 v oscillator / pll supply voltage v dda_osc_pll - 0.3 4.0 v internal logic core supply voltage v dd_core ocr_dis is high - 0.3 3.0 v input voltage (digital) v in pin groups 1, 2, 5, 6, 9, 10 -0.3 6.0 v input voltage (analog) v ina pin groups 11, 12, 13 -0.3 4.0 v output voltage v out pin groups 1, 2, 3, 4, 5, 6, 7, 8 -0.3 4.0 6.0 1 1. if corresponding gpio pin is configured as open drain. v output voltage (open drain) v od pin group 4 -0.3 6.0 v ambient temperature (automotive) t a -40 125 c ambient temperature (industrial) t a -40 105 c junction temperature (automotive) t j -40 150 c junction temperature (industrial) t j -40 125 c storage temperature (automotive) t stg -55 150 c storage temperature (industrial) t stg -55 150 c
56f8366 technical data, rev. 2.0 146 freescale semiconductor preliminary 1. theta-ja determined on 2s2p test boards is frequently lower than would be observed in an application. determined on 2s2p the r- mal test board. 2. junction to ambient thermal resistance, theta-ja (r ja ) was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal plan es (2s2p, where ?s? is the number of signal layers and ?p? is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction to case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the "resistance" from junction to reference point thermocouple on top cen- ter of case as defined in jesd51-2. jt is a useful value to use to estimate junction temperature in steady-state customer en- vironments. 5. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperatu re, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see part 12.1 for more details on thermal design considerations. 7. tj = junction temperature ta = ambient temperature table 10-2 56f8366/56f8166 electrostatic discharge (esd) protection characteristic min typ max unit esd for human body model (hbm) 2000 ? ? v esd for machine model (mm) 200 ? ? v esd for charge device model (cdm) 500 ? ? v table 10-3 thermal characteristics 6 characteristic comments symbol value unit notes 144-pin lqfp junction to ambient natural convection r ja 47.1 c/w 2 junction to ambient (@1m/sec) r jma 43.8 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 40.8 c/w 1,2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 39.2 c/w 1,2 junction to case r jc 11.8 c/w 3 junction to center of case jt 1c/w4, 5 i/o pin power dissipation p i/o user-determined w power dissipation p d p d = (i dd x v dd + p i/o )w maximum allowed p d p dmax (tj - ta) / r ja 7 w
general characteristics 56f8366 technical data, rev. 2.0 freescale semiconductor 147 preliminary note: the 56f8166 device is guaranteed to 40mhz and specified to meed industrial requirements only; can is not available on the 56f8166 device. note: total chip source or sink current cannot exceed 200 ma see pin groups in table 10-1 . table 10-4 recommended operating conditions (v reflo = 0v, v ss = v ssa_adc = 0v , v dda = v dda_adc = v dda_osc_pll ) characteristic symbol notes min typ max unit supply voltage v dd_io 33.33.6 v adc supply voltage v dda_adc, v refh v refh must be less than or equal to v dda_adc 33.33.6 v oscillator / pll supply voltage v dda_osc _pll 33.33.6 v internal logic core supply voltage v dd_core ocr_dis is high 2.25 2.5 2.75 v device clock frequency fsysclk 0? 60 mhz input high voltage (digital) v in pin groups 1, 2, 5, 6, 9, 10 2?5.5 v input high voltage (analog) v iha pin group 13 2?v dda +0.3 v input high voltage (xtal/extal, xtal is not driven by an external clock) v ihc pin group 11 v dda -0.8 ? v dda +0.3 v input high voltage (xtal/extal, xtal is driven by an external clock) v ihc pin group 11 2?v dda +0.3 v input low voltage v il pin groups 1, 2, 5, 6, 9, 10, 11, 13 -0.3 ? 0.8 v output high source current v oh = 2.4v (v oh min.) i oh pin groups 1, 2, 3 ?? -4 ma pin groups 5, 6, 7 ?? -8 pin group 8 ?? -12 output low sink current v ol = 0.4v (v ol max) i ol pin groups 1, 2, 3, 4 ?? 4 ma pin groups 5, 6, 7 ?? 8 pin group 8 ?? 12 ambient operating temperature (automotive) t a -40 ? 125 - (r ja x p d ) c ambient operating temperature (industrial) t a -40 ? 105 - (r ja x p d ) c flash endurance (automotive) (program erase cycles) n f t a = -40c to 125c 1000 ? ? cycles flash endurance (industrial) (program erase cycles) n f t a = -40c to 105c 1000 ? ? cycles flash data retention t r t j <= 85c avg 15 ? ? years
56f8366 technical data, rev. 2.0 148 freescale semiconductor preliminary 10.2 dc electrical characteristics note: the 56f8166 device is specified to meet i ndustrial requirements only; can is not available on the 56f8166 device. see pin groups in table 10-1 table 10-5 dc electrical characteristics at recommended operating conditions; see table 10-4 characteristic symbol notes min typ max unit test conditions output high voltage v oh 2.4 ? ? vi oh = i ohmax output low voltage v ol ??0.4 vi ol = i olmax digital input current high pull-up enabled or disabled i ih pin groups 1, 2, 5, 6, 9 ?0+/- 2.5 av in = 3.0v to 5.5v digital input current high with pull-down i ih pin group 10 40 80 160 av in = 3.0v to 5.5v analog input current high i iha pin group 13 ?0+/- 2.5 av in = v dda adc input current high i ihadc pin group 12 ?0+/- 3.5 av in = v dda digital input current low pull-up enabled i il pin groups 1, 2, 5, 6, 9 -200 -100 -50 av in = 0v digital input current low pull-up disabled i il pin groups 1, 2, 5, 6, 9 ?0+/- 2.5 av in = 0v digital input current low with pull-down i il pin group 10 ?0+/- 2.5 av in = 0v analog input current low i ila pin group 13 ?0+/- 2.5 av in = 0v adc input current low i iladc pin group 12 ?0+/- 3.5 av in = 0v extal input current low clock input i extal ?0+/- 2.5 av in = v dda or 0v xtal input current low clock input i xtal clkmode = high ?0+/- 2.5 av in = v dda or 0v clkmode = low ??200 av in = v dda or 0v output current high impedance state i oz pin groups 1, 2, 3, 4, 5, 6, 7, 8 ?0+/- 2.5 av out = 3.0v to 5.5v or 0v schmitt trigger input hysteresis v hys pin groups 2, 6, 9,10 ?0.3? v ? input capacitance (extal/xtal) c inc ?4.5? pf ? output capacitance (extal/xtal) c outc ?5.5? pf ? input capacitance c in ?6? pf ? output capacitance c out ?6? pf ?
dc electrical characteristics 56f8366 technical data, rev. 2.0 freescale semiconductor 149 preliminary table 10-6 power on reset low voltage parameters characteristic symbol min typ max units por trip point por 1.75 1.8 1.9 v lvi, 2.5 volt supply, trip point 1 1. when v dd_core drops below v ei2.5 , an interrupt is generated. v ei2.5 ?2.14? v lvi, 3.3 volt supply, trip point 2 2. when v dd_core drops below v ei3.3 , an interrupt is generated. v ei3.3 ?2.7? v bias current i bias ? 110 130 a table 10-7 current consumption per power supply pin (typical) on-chip regulator enabled (ocr_dis = low) mode i dd_io 1 1. no output switching 2. includes processor core current supplied by internal voltage regulator i dd_adc i dd_osc_pll test conditions run1_mac 155ma 50ma 2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? all peripherals running ? continuous mac instructions with fetches from data ram ? adc powered on and clocked wait3 91ma 70 a2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? adc powered off stop1 6ma 0 a165 a ? 8mhz device clock ? all peripheral clocks are off ? adc powered off ? pll powered off stop2 5.1ma 0 a155 a ? external clock is off ? all peripheral clocks are off ? adc powered off ? pll powered off
56f8366 technical data, rev. 2.0 150 freescale semiconductor preliminary table 10-8 current consumption per power supply pin (typical) on-chip regulator disabled (ocr_dis = high) mode i dd_core i dd_io 1 1. no output switching i dd_adc i dd_osc_pll test conditions run1_mac 150ma 13 a50ma 2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? all peripherals running ? continuous mac instructions with fetches from data ram ? adc powered on and clocked wait3 86ma 13 a70 a2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? adc powered off stop1 950 a13 a0 a165 a ? 8mhz device clock ? all peripheral clocks are off ? adc powered off ? pll powered off stop2 100 a13 a0 a155 a ? external clock is off ? all peripheral clocks are off ? adc powered off ? pll powered off table 10-9. regulator parameters characteristic symbol min typical max unit unloaded output voltage (0ma load) v rnl 2.25 ? 2.75 v loaded output voltage (200ma load) v rl 2.25 ? 2.75 v line regulation @ 250ma load (v dd 33 ranges from 3.0v to 3.6v) v r 2.25 ? 2.75 v short circuit current ( output shorted to ground) iss ? ? 700 ma bias current i bias ?5.8 7 ma power-down current i pd ?0 2 a short-circuit tolerance (output shorted to ground) t rsc ? ? 30 minutes
dc electrical characteristics 56f8366 technical data, rev. 2.0 freescale semiconductor 151 preliminary 10.2.1 temperature sensor note: temperature sensor is not available in the 56f8166 device. table 10-10. pll parameters characteristics symbol min typical max unit pll start-up time t ps 0.3 0.5 10 ms resonator start-up time t rs 0.1 0.18 1 ms min-max period variation t pv 120 ? 200 ps peak-to-peak jitter t pj ? ? 175 ps bias current i bias ?1.5 2 ma quiescent current, power-down mode i pd ? 100 150 a table 10-11 temperature sense parametrics characteristics symbol min typical max unit slope (gain) 1 m ? 7.762 ? mv/c room trim temp. 1, 2 1. includes the adc conversion of the analog temperature sense voltage. 2. the adc is not calibrated for the conv ersion of the temperature sensor trim value stored in the flash memory at fmopt0 and fmopt1. t rt 24 26 28 c hot trim temp. (industrial) 1,2 t ht 122 125 128 c hot trim temp. (automotive) 1,2 t ht 147 150 153 c output voltage @ v dda_adc = 3.3v, t j =0c 1 v ts0 ? 1.370 ? v supply voltage v dda_adc 3.0 3.3 3.6 v supply current - off i dd-off ??10 a supply current - on i dd-on ??250 a accuracy 3,1 from -40c to 150c using v ts = mt + v ts0 3. see application note, an1980, for methods to increase accuracy. t acc -6.7 0 6.7 c resolution 4, 5,1 4. assuming a 12-bit range from 0v to 3.3v. 5. typical resolution calculated using equation, r es = (v refh - v reflo ) x 1 2 12 m r es ? 0.104 ? c / bit
56f8366 technical data, rev. 2.0 152 freescale semiconductor preliminary 10.3 ac electrical characteristics tests are conducted using the input levels specified in table 10-5 . unless otherwise specified, propagation delays are measured from the 50% to th e 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 10-1 . figure 10-1 input signal measurement references figure 10-2 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 10-2 signal states 10.4 flash memory characteristics table 10-12 flash timing parameters characteristic symbol min typ max unit program time 1 1. there is additional overhead which is part of the programming sequence. see the 56f8300 peripheral user manual for details. program time is per 16-bit word in flash memory. two words at a time can be programmed within the pro- gram flash module, as it contains two interleaved memories. t prog 20 ? ? s erase time 2 2. specifies page erase time. there are 512 bytes per page in the data and boot flash memories. the program flash module uses two interleaved flash memories, increasing the effective page size to 1024 bytes. t erase 20 ? ? ms mass erase time t me 100 ? ? ms v ih v il fall time input signal note: the midpoint is v il + (v ih ? v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
external clock operation timing 56f8366 technical data, rev. 2.0 freescale semiconductor 153 preliminary 10.5 external clock operation timing figure 10-3 external clock timing 10.6 phase locked loop timing table 10-13 external clock operation timing requirements 1 1. parameters listed are guaranteed by design. characteristic symbol min typ max unit frequency of operation (external clock driver) 2 2. see figure 10-3 for details on using the recommended connection of an external clock driver. f osc 0?120mhz clock pulse width 3 3. the high or low pulse width must be no smaller than 8.0ns or the chip will not function. t pw 3.0 ? ? ns external clock input rise time 4 4. external clock input rise time is measured from 10% to 90%. t rise ??10ns external clock input fall time 5 5. external clock input fall time is measured from 90% to 10%. t fall ??10ns table 10-14 pll timing characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. f osc 488mhz pll output frequency 2 (f out ) 2. zclk may not exceed 60mhz. for additional information on zclk and (f out /2), please refer to the occs chapter in the 56f8300 peripheral user manual . f op 160 ? 260 mhz pll stabilization time 3 -40 to +125 c 3. this is the minimum time required after the pll set up is changed to ensure reliable operation. t plls ?110ms external clock v ih v il note: the midpoint is v il + (v ih ? v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
56f8366 technical data, rev. 2.0 154 freescale semiconductor preliminary 10.7 crystal oscillator timing 10.8 external memory interface timing the external memory interface is designed to access static memory and peripheral devices. figure 10-4 shows sample timing and parame ters that are detailed in table 10-16 . the timing of each parameter consists of both a fixe d delay portion and a clock related portion, as well as user controlled wait states. the equation: t = d + p * (m + w) should be used to determine the actual time of each parameter. the terms in this equation are defined as: when using the xtal clock input directly as the chip clock without presca ling (zsrc selects prescaler clock and prescaler is set to 1), the emi quadrature clock is generated using both edges of the extal table 10-15 crystal oscillator parameters characteristic symbol min typ max unit crystal start-up time t cs 4510ms resonator start-up time t rs 0.1 0.18 1 ms crystal esr r esr ? ? 120 ohms crystal peak-to-peak jitter t d 70 ? 250 ps crystal min-max period variation t pv 0.12 ? 1.5 ns resonator peak-to-peak jitter t rj ? ? 300 ps resonator min-max period variation t rp ? ? 300 ps bias current, high-drive mode i biash ? 250 290 a bias current, low-drive mode i biasl ? 80 110 a quiescent current, power-down mode i pd ?0 1 a t = parameter delay time d = fixed portion of the delay, due to on-chip path delays p = period of the system clock, which determines the execution rate of the part (i.e., when the device is operating at 60mhz, p = 16.67 ns) m = fixed portion of a clock period inherent in the design; this number is adjusted to account for possible derating of clock duty cycle w = sum of the applicable wait state controls. the ?wait state controls? column of table 10-16 shows the applicable controls for each parameter and the emi chapter of the 56f8300 peripheral user manual details what each wait state field controls.
external memory interface timing 56f8366 technical data, rev. 2.0 freescale semiconductor 155 preliminary clock input. in this situation only, parameter values must be adjusted for the duty cycle at xtal. dcaoe and dcaeo are used to make this duty cycle adjustment where needed. dcaoe and dcaeo are calculated as follows: the timing of write cycles is different when wws = 0 than when wws > 0. therefore, some parameters contain two sets of numbers to account for this diff erence. use the ?wait states configuration? column of table 10-16 to make the appropriate selection. figure 10-4 external memory interface timing note: when multiple lines are given for the same wait state configuration, calculate each and then select the smallest or most negative. dcaoe = = 0.5 - max xtal duty cycle, if zsrc selects prescaler clock and the prescaler is set to 1 0.0 all other cases dcaeo = = min xtal duty cycle - 0.5, if zsrc selects prescaler clock and the prescaler is set to 1 0.0 all other cases example of dcaoe and dcaeo calculation: assuming prescaler is set for 1 and prescaler clock is selected by zsrc, if xtal duty cycle ranges between 45% and 60% high: dcaoe = .50 - .60 = - 0.1 dcaeo = .45 - .50 = - 0.05 t drd t rdd t ad t doh t dos t dwr t rdwr t wac t wrrd t wr t awr t wrwr t ardd t rda t rdrd t rd t arda data out data in a0-axx,cs rd wr d0-d15 note: during read-modify-write instructions and inter nal instructions, the address lines do not change state.
56f8366 technical data, rev. 2.0 156 freescale semiconductor preliminary table 10-16 external memory interface timing characteristic symbol wait states configuration dm wait states controls unit address valid to wr asserted t awr wws=0 -2.076 0.50 wwss ns wws>0 -1.795 0.75 + dcaoe wr width asserted to wr deasserted t wr wws=0 -0.094 0.25 + dcaoe wws ns wws>0 -0.012 0 data out valid to wr asserted t dwr wws=0 -9.321 0.25 + dcaeo wwss ns wws=0 -1.160 0.00 wws>0 -8.631 0.50 wws>0 -0.879 0.25 + dcaoe valid data out hold time after wr deasserted t doh -2.086 0.25 + dcaeo wwsh ns valid data out set up time to wr deasserted t dos -0.563 0.25 + dcaoe wws,wwss ns -8.315 0.50 valid address after wr deasserted t wac -3.432 0.25 + dcaeo wwsh ns rd deasserted to address invalid t rda -1.780 0.00 rwsh ns address valid to rd deasserted t ardd -2.120 1.00 rwss,rws ns valid input data hold after rd deasserted t drd 0.00 n/a 1 1. n/a, since device captures data before it deasserts rd ? ns rd assertion width t rd 0.279 1.00 rws ns address valid to input data valid t ad -15.723 1.00 rwss,rws ns -20.642 1.25 + dcaoe address valid to rd asserted t arda -2.603 0.00 rwss ns rd asserted to input data valid t rdd -13.120 1.00 rwss,rws ns -18.039 1.25 + dcaoe wr deasserted to rd asserted t wrrd -2.135 0.25 + dcaeo wwsh,rwss ns rd deasserted to rd asserted t rdrd -0.483 2 2. if rwss = rwsh = 0, and the chip select does not change, then r d does not deassert during back-to-back reads. 0.00 rwss,rwsh mdar 3 , 4 3. substitute bmdar for mdar if there is no chip select 4. mdar is active in this calculation only when the chip select changes. ns wr deasserted to wr asserted t wrwr wws=0 -1.608 0.75 + dcaeo wwss, wwsh ns wws>0 -0.918 1.00 rd deasserted to wr asserted t rdwr wws=0 -0.096 0.50 rwsh, wwss, mdar 3 ns wws>0 0.084 0.75 + dcaoe
reset, stop, wait, mode select, and interrupt timing 56f8366 technical data, rev. 2.0 freescale semiconductor 157 preliminary 10.9 reset, stop, wait, mode select, and interrupt timing figure 10-5 asynchronous reset timing table 10-17 reset, stop, wait, mode select, and interrupt timing 1,2 1. in the formulas, t = clock cycle. for an operating frequency of 60mhz, t = 16.67ns. at 8mhz (used during reset and stop modes), t = 125ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit see figure reset assertion to address, data and control signals high impedance t raz ?21ns 10-5 minimum reset assertion duration t ra 16t ? ns 10-5 reset deassertion to first external address output 3 3. during power-on reset, it is possible to use the device?s internal reset stretching circuitry to extend this period to 2 21 t. t rda 63t 64t ns 10-5 edge-sensitive interrupt request width t irw 1.5t ? ns 10-6 irqa , irqb assertion to external data memory access out valid, caused by first instruction execution in the interrupt service routine t idm 18 ? ns 10-7 t idm - fast 14 ? irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 18 ? ns 10-7 t ig - fast 14 ? delay from irqa assertion (exiting wait) to external data memory access 4 4. the minimum is specified for the duration of an edge-sensitive irqa interrupt required to recover from the stop state. this is not the minimum required so that the irqa interrupt is accepted. t iri 22 ? ns 10-8 t iri -fast 18 ? delay from irqa assertion to external data memory access (exiting stop) t if 22 ? ns 10-9 t if - fast 18 ? irqa width assertion to recover from stop state 5 5. the interrupt instruction fetch is visible on the pins only in mode 3. t iw 1.5t ? ns 10-9 first fetch t ra t raz t rda a0?a15 , d0?d15 reset
56f8366 technical data, rev. 2.0 158 freescale semiconductor preliminary figure 10-6 external interrupt ti ming (negative edge-sensitive) figure 10-7 external level-sensitive interrupt timing figure 10-8 interrupt from wait state timing irqa , irqb t irw t idm a0?a15 irqa , irqb first interrupt instruction execution a) first interrupt instruction execution t ig general purpose i/o pin irqa , irqb b) general purpose i/o instruction fetch t iri irqa , irqb first interrupt vector a0?a15
serial peripheral interface (spi) timing 56f8366 technical data, rev. 2.0 freescale semiconductor 159 preliminary figure 10-9 recovery from stop stat e using asynchronous interrupt timing 10.10 serial peripheral interface (spi) timing table 10-18 spi timing 1 characteristic symbol min max unit see figure cycle time master slave t c 50 50 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 enable lead time master slave t eld ? 25 ? ? ns ns 10-13 enable lag time master slave t elg ? 100 ? ? ns ns 10-13 clock (sck) high time master slave t ch 17.6 25 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 clock (sck) low time master slave t cl 24.1 25 ? ? ns ns 10-13 data set-up time required for inputs master slave t ds 20 0 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 data hold time required for inputs master slave t dh 0 2 ? ? ns ns 10-10 , 10-11 , 10-12 , 10-13 access time (time to data active from high-impedance state) slave t a 4.8 15 ns 10-13 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns 10-13 data valid for outputs master slave (after enable edge) t dv ? ? 4.5 20.4 ns ns 10-10 , 10-11 , 10-12 , 10-13 not irqa interrupt vector t iw irqa t if a0?a15 first instruction fetch
56f8366 technical data, rev. 2.0 160 freescale semiconductor preliminary figure 10-10 spi master timing (cpha = 0) data invalid master slave t di 0 0 ? ? ns ns 10-10 , 10-11 , 10-12 rise time master slave t r ? ? 11.5 10.0 ns ns 10-10 , 10-11 , 10-12 , 10-13 fall time master slave t f ? ? 9.7 9.0 ns ns 10-10 , 10-11 , 10-12 , 10-13 1. parameters listed are guaranteed by design. table 10-18 spi timing 1 (continued) characteristic symbol min max unit see figure sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14?1 master lsb out ss (input) t ch ss is held high on master t f
serial peripheral interface (spi) timing 56f8366 technical data, rev. 2.0 freescale semiconductor 161 preliminary figure 10-11 spi master timing (cpha = 1) figure 10-12 spi slave timing (cpha = 0) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14?1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14? 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t f t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r
56f8366 technical data, rev. 2.0 162 freescale semiconductor preliminary figure 10-13 spi slave timing (cpha = 1) 10.11 quad timer timing table 10-19 timer timing 1, 2 1. in the formulas listed, t = the clock cycle. for 60mhz operation, t = 16.67ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ? ns 10-14 timer input high / low period p inhl 1t + 3 ? ns 10-14 timer output period p out 1t - 3 ? ns 10-14 timer output high / low period p outhl 0.5t - 3 ? ns 10-14 sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14?1 t c t cl t cl t ch t di msb in bits 14?1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
quadrature decoder timing 56f8366 technical data, rev. 2.0 freescale semiconductor 163 preliminary figure 10-14 timer timing 10.12 quadrature decoder timing figure 10-15 quadrature decoder timing table 10-20 quadrature decoder timing 1, 2 1. in the formulas listed, t = the clock cycle. for 60mhz operation, t = 16.67ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure quadrature input period p in 4t + 12 ? ns 10-15 quadrature input high / low period p hl 2t + 6 ? ns 10-15 quadrature phase period p ph 1t + 3 ? ns 10-15 p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs phase b (input) p in p hl p hl phase a (input) p in p hl p hl p ph p ph p ph p ph
56f8366 technical data, rev. 2.0 164 freescale semiconductor preliminary 10.13 serial communication interface (sci) timing figure 10-16 rxd pulse width figure 10-17 txd pulse width 10.14 controller area network (can) timing note: can is not available in the 56f8166 device. table 10-21 sci timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2. f max is the frequency of operation of the system clock, zclk, in mhz, which is 60mhz for the 56f8366 device and 40mhz for the 56f8166 device.. br ? (f max /16) mbps ? rxd 3 pulse width 3. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns 10-16 txd 4 pulse width 4. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. txd pw 0.965/br 1.04/br ns 10-17 table 10-22 can timing 1 1. parameters listed are guaranteed by design characteristic symbol min max unit see figure baud rate br can ? 1mbps ? bus wake up detection t wakeup 5 ? s 10-18 rxd pw rxd sci receive data pin (input) txd pw txd sci receive data pin (input)
jtag timing 56f8366 technical data, rev. 2.0 freescale semiconductor 165 preliminary figure 10-18 bus wake up detection 10.15 jtag timing figure 10-19 test clock input timing diagram table 10-23 jtag timing characteristic symbol min max unit see figure tck frequency of operation using eonce 1 1. tck frequency of operation must be less than 1/8 the processor rate. f op dc sys_clk/8 mhz 10-19 tck frequency of operation not using eonce 1 f op dc sys_clk/4 mhz 10-19 tck clock pulse width t pw 50 ? ns 10-19 tms, tdi data set-up time t ds 5? ns 10-20 tms, tdi data hold time t dh 5? ns 10-20 tck low to tdo data valid t dv ?30 ns 10-20 tck low to tdo tri-state t ts ?30 ns 10-20 trst assertion time t trst 2t 2 2. t = processor clock period (nominally 1/60mhz) ?ns 10-21 t wakeup can_rx can receive data pin (input) tck (input) v m v il v m = v il + (v ih ? v il )/2 t pw 1/f op t pw v m v ih
56f8366 technical data, rev. 2.0 166 freescale semiconductor preliminary figure 10-20 test access port timing diagram figure 10-21 trst timing diagram 10.16 analog-to-digital converter (adc) parameters table 10-24 adc parameters characteristic symbol min typ max unit input voltages v adin v refl ?v refh v resolution r es 12 ? 12 bits integral non-linearity 1 inl ? +/- 2.4 +/- 3.2 lsb 2 differential non-linearity dnl ? +/- 0.7 < +1 lsb 2 monotonicity guaranteed adc internal clock f adic 0.5 ? 5 mhz conversion range r ad v refl ?v refh v adc channel power-up time t adpu 5616 t aic cycles 3 input data valid output data valid output data valid t ds t dh t dv t ts t dv tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms trst (input) t trst
analog-to-digital converter (adc) parameters 56f8366 technical data, rev. 2.0 freescale semiconductor 167 preliminary adc reference circuit power-up time 4 t vref ??25ms conversion time t adc ?6? t aic cycles 3 sample time t ads ?1? t aic cycles 3 input capacitance c adi ?5?pf input injection current 5 , per pin i adi ?? 3ma input injection current, total i adit ??20ma v refh current i vrefh ?1.2 3ma adc a current i adca ?25?ma adc b current i adcb ?25?ma quiescent current i adcq ?010 a uncalibrated gain error (ideal = 1) e gain ? +/- .004 +/- .01 ? uncalibrated offset voltage v offset ?+/- 27+/- 40mv calibrated absolute error 6 ae cal ?see figure 10-22 ?lsbs calibration factor 1 7 cf1 ? 0.002289 ? ? calibration factor 2 cf2 ? -25.6 ? ? crosstalk between channels ? ? -60 ? db common mode voltage v common ?(v refh - v reflo ) / 2 ? v signal-to-noise ratio snr ? 64.6 ? db signal-to-noise plus distortion ratio sinad ? 59.1 ? db total harmonic distortion thd ? 60.6 ? db spurious free dynamic range sfdr ? 61.1 ? db effective number of bits 8 enob ? 9.6 ? bits 1. inl measured from v in = .1v refh to v in = .9v refh 10% to 90% input signal range 2. lsb = least significant bit 3. adc clock cycles 4. assumes each voltage reference pin is bypassed with 0.1 f ceramic capacitors to ground 5. the current that can be injected or sourced from an unselected adc signal input without impacting the performance of the adc. this allows the adc to operate in noisy industrial environments where inductive flyback is possible. 6. absolute error includes the effects of both gain error and offset error. 7. please see the 56f8300peripheral user?s manual for additional information on adc calibration. 8. enob = (sinad - 1.76)/6.02 table 10-24 adc parameters (continued) characteristic symbol min typ max unit
56f8366 technical data, rev. 2.0 168 freescale semiconductor preliminary figure 10-22 adc absolute error over processing and temperature extremes before and after calibration for vdc in = 0.60v and 2.70v note: the absolute error data shown in the graphs above reflects the effects of both gain error and offset error. the data was taken on 25 parts: five each from four processing corner lots as well as five from one nominally processed lot, each at three temperatur es: -40c, 27c, and 150c (giving the 75 data points shown above), for two input dc voltages: 0.60v a nd 2.70v. the data indicates that for the given population of parts, calibration significantly reduced (by as much as 24%) the collective variation (spread) of the absolute error of the population. it also significantly reduced (by as much as 38%) the mean (average) of the absolute error and thereby brought it significantly closer to the ideal value of zero. although not guaranteed, it is believed that calibrati on will produce results similar to those shown above for any population of parts including those which represent processing and temperature extremes.
equivalent circuit for adc inputs 56f8366 technical data, rev. 2.0 freescale semiconductor 169 preliminary 10.17 equivalent circuit for adc inputs figure 10-23 illustrates the adc input circuit during samp le and hold. s1 and s2 are always open/closed at the same time that s3 is closed/open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to v refh - v refh / 2, while the other charges to the analog input voltage. when the switches are flipped, the charge on c1 and c2 are av eraged via s3, with the result that a single-ended analog input is switched to a differential voltage centered about v refh - v refh / 2. the switches switch on every cycle of the adc clock (open one-half adc clock, closed one-half adc clock). note that there are additional capacitances associated with the anal og input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 provides is olation during the charge-sharing phase. one aspect of this circuit is that there is an on-goi ng input current, which is a function of the analog input voltage, v ref and the adc clock frequency. 1. parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the esd isolation resistor and the channel select mux; 500 ohms 4. sampling capacitor at the sample and hold circuit. capa citor c1 is normally disconnected from the input and is only connected to it at sampling time; 1pf figure 10-23 equivalent circuit for a/d loading 10.18 power consumption this section provides additional detail which can be used to optimize power consumption for a given application. power consumption is given by the following equation: a, the internal [static component], is comprised of th e dc bias currents for the oscillator, leakage current, pll, and voltage references. these sources operate independently of proc essor state or operating frequency. total power = a: internal [static component] +b: internal [state-dependent component] +c: internal [dynamic component] +d: external [dynamic component] +e: external [static] 1 2 3 analog input 4 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf (v refh - v reflo ) / 2
56f8366 technical data, rev. 2.0 170 freescale semiconductor preliminary b, the internal [state-dependent component], re flects the supply current required by certain on-chip resources only when those resources are in use. these include ram, flash memory and the adcs. c, the internal [dynamic component], is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic component], reflects power di ssipated on-chip as a result of capacitive loading on the external pins of the chip. this is also commonly described as c*v 2 *f, although simulations on two of the io cell types used on the device reveal that the power-versus-load curve does have a non-zero y-intercept. power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. table 10-25 provides coefficients for calculating power dissipated in the io cells as a function of capacitive load. in these cases: totalpower = ((intercept +slope*cload)*frequency/10mhz) where: ? summation is performed over all output pins with capacitive loads ? totalpower is expressed in mw ? cload is expressed in pf because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. the one possible exception to this is if the chip is using the external address and data buses at a rate approaching the maximum system rate. in this case, power from these buses can be significant. e, the external [static component], reflects the effe cts of placing resistive loads on the outputs of the device. sum the total of all v 2 /r or iv to arrive at the resistive load contribution to power. assume v = 0.5 for the purposes of these rough calculations. for inst ance, if there is a total of 8 pwm outputs driving 10ma into leds, then p = 8*.5*.01 = 40mw. in previous discussions, power consumption due to pa rasitics associated with pure input pins is ignored, as it is assumed to be negligible. table 10-25 io loading coefficients at 10mhz intercept slope pdu08dgz_me 1.3 0.11mw / pf pdu04dgz_me 1.15mw 0.11mw / pf
56f8366 package and pin-out information 56f8366 technical data, rev. 2.0 freescale semiconductor 171 preliminary part 11 packaging 11.1 56f8366 package and pin-out information this section contains package and pin-out informat ion for the 56f8366. this device comes in a 144-pin low-profile quad flat pack (lqfp). figure 11-1 shows the package outline for the lqfp, figure 11-3 shows the mechanical parameters for this package, and table 11-1 lists the pin-out for the 144-pin lqfp. figure 11-1 top view, 56f8366 144-pin lqfp package v dd_io v pp 2 clko txd0 rxd0 phasea1 phaseb1 index1 home1 a1 a2 a3 a4 a5 v cap 4 v dd_io a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 v ss d7 d8 d9 v dd_io d10 gpiob0 pwmb0 pwmb1 pwmb2 v ss v dd_io pwmb3 pwmb4 pwmb5 txd1 rxd1 wr rd ps ds gpiod0 gpiod1 isb0 v cap 1 isb1 isb2 irqa irqb faultb0 faultb1 faultb2 d0 d1 faultb3 pwma0 v ss pwma1 pwma2 v dd_io pwma3 pwma4 v ss pwma5 faulta0 d2 faulta1 faulta2 d3 d4 d5 d6 ocr_dis v dda_osc_pll xtal extal v cap 3 v dd_io rsto reset clkmode ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 temp_sense v reflo v refn v refmid v refp v refh v dda_adc v ssa_adc anb0 anb1 anb2 anb3 anb4 anb5 anb6 anb7 extboot isa0 isa1 isa2 td0 td1 tc0 v dd_io trst tck tms tdi tdo v pp i can_tx can_rx v cap 2 ss0 sclk0 miso0 mosi0 d11 d12 d13 d14 d15 a0 phasea0 phaseb0 index0 home0 emi_mode v ss pin 1 orientation mark 73 109 37
56f8366 technical data, rev. 2.0 172 freescale semiconductor preliminary table 11-1 56f8366 144-pin lqfp package identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v dd_io 37 v ss 73 faulta1 109 anb5 2v pp 238 v dd_io 74 faulta2 110 anb6 3 clko 39 pwmb3 75 d3 111 anb7 4 txd0 40 pwmb4 76 d4 112 extboot 5 rxd0 41 pwmb5 77 d5 113 isa0 6 phasea1 42 txd1 78 d6 114 isa1 7 phaseb1 43 rxd1 79 ocr_dis 115 isa2 8 index1 44 wr 80 v dda_osc_pll 116 td0 9home145 rd 81 xtal 117 td1 10 a1 46 ps 82 extal 118 tc0 11 a2 47 ds 83 v cap 3119v dd_io 12 a3 48 gpiod0 84 v dd_io 120 trst 13 a4 49 gpiod1 85 rsto 121 tck 14 a5 50 isb0 86 reset 122 tms 15 v cap 451 v cap 187 clkmode123 tdi 16 v dd_io 52 isb1 88 ana0 124 tdo 17 a6 53 isb2 89 ana1 125 v pp 1 18 a7 54 irqa 90 ana2 126 can_tx 19 a8 55 irqb 91 ana3 127 can_rx 20 a9 56 faultb0 92 ana4 128 v cap 2 21 a10 57 faultb1 93 ana5 129 ss0 22 a11 58 faultb2 94 ana6 130 sclk0 23a1259d095 ana7 131miso0 24 a13 60 d1 96 temp_sense 132 mosi0 25 a14 61 faultb3 97 v reflo 133 d11
56f8366 package and pin-out information 56f8366 technical data, rev. 2.0 freescale semiconductor 173 preliminary 26 a15 62 pwma0 98 v refn 134 d12 27 v ss 63 v ss 99 v refmid 135 d13 28 d7 64 pwma1 100 v refp 136 d14 29 d8 65 pwma2 101 v refh 137 d15 30 d9 66 v dd_io 102 v dda_adc 138 a0 31 v dd_io 67 pwma3 103 v ssa_adc 139 phasea0 32 d10 68 pwma4 104 anb0 140 phaseb0 33 gpiob0 69 v ss 105 anb1 141 index0 34 pwmb0 70 pwma5 106 anb2 142 home0 35 pwmb1 71 faulta0 107 anb3 143 emi_mode 36 pwmb2 72 d2 108 anb4 144 v ss table 11-1 56f8366 144-pin lqfp package identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name
56f8366 technical data, rev. 2.0 174 freescale semiconductor preliminary 11.2 56f8166 package and pin-out information this section contains package and pin-out inform ation for the 56f8166. this device comes in a 144-pin low-profile quad flat pack (lqfp). figure 11-1 shows the package outline for the lqfp ; figure 11-3 shows the mechanical parameters for this package, and table 11-1 lists the pin-out for the 144-pin lqfp. figure 11-2 top view, 56f8166 144-pin lqfp package v dd_io v pp 2 clko txd0 rxd0 sclk1 mosi1 miso1 ss1 a1 a2 a3 a4 a5 v cap 4 v dd_io a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 v ss d7 d8 d9 v dd_io d10 gpiob0 pwmb0 pwmb1 pwmb2 v ss v dd_io pwmb3 pwmb4 pwmb5 txd1 rxd1 wr rd ps ds gpiod0 gpiod1 isb0 v cap 1 isb1 isb2 irqa irqb faultb0 faultb1 faultb2 d0 d1 faultb3 nc v ss nc nc v dd_io nc nc v ss nc nc d2 nc nc d3 d4 d5 d6 ocr_dis v dda_osc_pll xtal extal v cap 3 v dd_io rsto reset clkmode ana0 ana1 ana2 ana3 ana4 ana5 ana6 ana7 nc v reflo v refn v refmid v refp v refh v dda_adc v ssa_adc anb0 anb1 anb2 anb3 anb4 anb5 anb6 anb7 extboot gpioc8 gpioc9 gpioc10 gpioe10 gpioe11 tc0 v dd_io trst tck tms tdi tdo v pp i nc nc v cap 2 ss0 sclk0 miso0 mosi0 d11 d12 d13 d14 d15 a0 phasea0 phaseb0 index0 home0 emi_mode v ss pin 1 orientation mark 73 109 37
56f8166 package and pin-out information 56f8366 technical data, rev. 2.0 freescale semiconductor 175 preliminary table 11-2 56f8166 144-pin lqfp package identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1v dd_io 37 v ss 73 nc 109 anb5 2v pp 238 v dd_io 74 nc 110 anb6 3 clko 39 pwmb3 75 d3 111 anb7 4 txd0 40 pwmb4 76 d4 112 extboot 5 rxd0 41 pwmb5 77 d5 113 gpioc8 6 sclk1 42 txd1 78 d6 114 gpioc9 7 mosi1 43 rxd1 79 ocr_dis 115 gpioc10 8miso144 wr 80 v dda_osc_pll 116 gpioe10 9 ss1 45 rd 81 xtal 117 gpioe11 10 a1 46 ps 82 extal 118 tc0 11 a2 47 ds 83 v cap 3119v dd_io 12 a3 48 gpiod0 84 v dd_io 120 trst 13 a4 49 gpiod1 85 rsto 121 tck 14 a5 50 isb0 86 reset 122 tms 15 v cap 451 v cap 187 clkmode123 tdi 16 v dd_io 52 isb1 88 ana0 124 tdo 17 a6 53 isb2 89 ana1 125 v pp 1 18 a7 54 irqa 90 ana2 126 nc 19 a8 55 irqb 91 ana3 127 nc 20 a9 56 faultb0 92 ana4 128 v cap 2 21 a10 57 faultb1 93 ana5 129 ss0 22 a11 58 faultb2 94 ana6 130 sclk0 23a1259d095 ana7 131miso0 24a1360d196 nc 132mosi0 25 a14 61 faultb3 97 v reflo 133 d11
56f8366 technical data, rev. 2.0 176 freescale semiconductor preliminary 26 a15 62 nc 98 v refn 134 d12 27 v ss 63 v ss 99 v refmid 135 d13 28 d7 64 nc 100 v refp 136 d14 29 d8 65 nc 101 v refh 137 d15 30 d9 66 v dd_io 102 v dda_adc 138 a0 31 v dd_io 67 nc 103 v ssa_adc 139 phasea0 32 d10 68 nc 104 anb0 140 phaseb0 33 gpiob0 69 v ss 105 anb1 141 index0 34 pwmb0 70 nc 106 anb2 142 home0 35 pwmb1 71 nc 107 anb3 143 emi_mode 36 pwmb2 72 d2 108 anb4 144 v ss table 11-2 56f8166 144-pin lqfp package identification by pin number (continued) pin no. signal name pin no. signal name pin no. signal name pin no. signal name
56f8166 package and pin-out information 56f8366 technical data, rev. 2.0 freescale semiconductor 177 preliminary figure 11-3 144-pin lqfp mechanical information please see www.freescale.com for the most current case outline. d 0.20 h b-c 144 gage plane 73 109 37 seating 108 1 36 72 plane 4x 4x 36 tips pin 1 index view a e1 e1/2 e/2 d1/2 d/2 e e/2 e d1 d 0.1 a 2 view b a a 140x 4x view a plating b1 c1 c b base metal section a-a (rotated 90 ) 144 places d 0.08 m ab-c dim d1 min max 20.00 bsc millimeters e1 20.00 bsc a --- 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.17 0.27 l 0.45 0.75 b1 0.17 0.23 e 0.50 bsc c 0.09 0.20 l2 0.50 ref r1 0.13 0.20 r2 0.13 --- d 22.00 bsc e 22.00 bsc s 0.25 ref l1 1.00 ref c1 0.09 0.16 0 7 0 --- 1 2 notes: 1. all dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums b, c and d to be determined at datum h. 4. the top package body size may be smaller than the bottom package size by a maximum of 0.1 mm. 5. dimensions d1 and e1 do not include mold protrusions. the maximum allowable protrusion is 0.25 mm per side. d1 and e1 are maximum body size dimensions including mold mismatch. 6. dimension b does not include dambar protrusion. protrusions shall not cause the lead width to exceed 0.35. minimum space between protrusion and an adjacent lead shall be 0.07 mm. 7. dimensions d and e to be determined at the seating plane, datum a. case 918 03 0.05 c l l1 r2 l a2 s r1 l2 a1 1 0.25 view b d 0.20 a b-c c b d a a 144x x x=b, c or d 8x 12 ref 4 top view 5 7 4 5 7 side view h 6 3
56f8366 technical data, rev. 2.0 178 freescale semiconductor preliminary part 12 design considerations 12.1 thermal design considerations an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r j x p d ) where: the junction-to-ambient thermal resistance is an i ndustry-standard value that provides a quick and easy estimation of thermal performance. unfortunately, th ere are two values in common usage: the value determined on a single-layer board and the value obtai ned on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single-layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r j = r j + r c where: r jc is device-related and cannot be influenced by the us er. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface ma terial, the mounting arrangement on printed circuit board, or change the thermal dissipation on th e printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where: t a = ambient temperature for the package ( o c) r j = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w t t = thermocouple temperature on top of package ( o c) jt = thermal characterization parameter ( o c)/w p d = power dissipation in package (w)
electrical design considerations 56f8366 technical data, rev. 2.0 freescale semiconductor 179 preliminary the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the pa ckage case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid m easurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of th e clearance is important to minimize the change in thermal performance caused by removi ng part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separa te measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 12.2 electrical design considerations use the following list of considerations to assure correct device operation: ? provide a low-impedance path from the board power supply to each v dd pin on the device, and from the board ground to each v ss (gnd) pin ? the minimum bypass requirement is to place six 0.01?0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacitors tend to provide better performance tolerances. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead ? use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and v ss ? bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with a high-grade capacitor such as a tantalum capacitor ? because the device?s output signals have fast rise and fall times, pcb trace lengths should be minimal caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56f8366 technical data, rev. 2.0 180 freescale semiconductor preliminary ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda and v ssa pins ? designs that utilize the trst pin for jtag port or eonce module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. ? because the flash memory is programmed through the jtag/eonce port, the designer should provide an interface to this port to allow in-circuit flash programming 12.3 power distribution and i/o ring implementation figure 12-1 illustrates the general power control in corporated in the 56f8366/56f8166. this chip contains two internal power regulators. one of them is powered from the v dda_osc_pll pin and cannot be turned off. this regulator controls power to th e internal clock generation circuitry. the other regulator is powered from the v dd_io pins and provides power to all of the internal digital logic of the core, all peripherals and the internal memories. this regul ator can be turned off, if an external v dd_core voltage is externally applied to the v cap pins. in summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is enabled. if the regulator is not enabled, a dual s upply 3.3v/2.5v configuration can also be used. notes: ? flash, ram and internal logic are powered from the core regulator output ?v pp 1 and v pp 2 are not connected in the customer system ? all circuitry, analog and digital, shares a common v ss bus figure 12-1 power management reg core v cap i/o adc v dd v ss reg v dda_osc_pll osc v ssa_adc v dda_adc v refh v refp v refmid v refn v reflo
power distribution and i/o ring implementation 56f8366 technical data, rev. 2.0 freescale semiconductor 181 preliminary part 13 ordering information table 13-1 lists the pertinent information needed to pl ace an order. consult a freescale semiconductor sales office or authorized distributor to determine availability and to order parts. *this package is rohs compliant. table 13-1 ordering information part supply voltage package type pin count frequency (mhz) temperature range order number mc56f8366 3.0?3.6 v low-profile quad flat pack (lqfp) 144 60 -40 to + 105 c mc56f8366vfv60 mc56f8366 3.0?3.6 v low-profile quad flat pack (lqfp) 144 60 -40 to + 125 c MC56F8366MFV60 mc56f8166 3.0?3.6 v low-profile quad flat pack (lqfp) 144 40 -40 to + 105 c mc56f8166vfv mc56f8366 3.0?3.6 v low-profile quad flat pack (lqfp) 144 60 -40 to + 105 c mc56f8366vfve* mc56f8366 3.0?3.6 v low-profile quad flat pack (lqfp) 144 60 -40 to + 125 c mc56f8366mfve* mc56f8166 3.0?3.6 v low-profile quad flat pack (lqfp) 144 40 -40 to + 105 c mc56f8166vfve*
56f8366 technical data, rev. 2.0 182 freescale semiconductor preliminary
power distribution and i/o ring implementation 56f8366 technical data, rev. 2.0 freescale semiconductor 183 preliminary
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